<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27523">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Update PMC base address for CNP H and LP<br><br>PMC base address is different for CNP LP pch and CNP H pch.<br>Added logic to determine PMC base addrress dynamically based on PCH ID.<br><br>BUG=none<br>BRANCH=none<br>TEST=none<br><br>Change-Id: I833395260e8fb631823bd03192a092df323250fa<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/soc/intel/cannonlake/bootblock/pch.c<br>M src/soc/intel/cannonlake/include/soc/lpc.h<br>2 files changed, 45 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/27523/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>index eb67012..e5bb8e6 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>@@ -27,12 +27,15 @@</span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/lpc.h></span><br><span> #include <soc/p2sb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pch.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pcr_ids.h></span><br><span> #include <soc/pm.h></span><br><span> #include <soc/smbus.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1400</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP 0x1400</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define PCR_PSFX_TO_SHDW_BAR0 0</span><br><span> #define PCR_PSFX_TO_SHDW_BAR1 0x4</span><br><span> #define PCR_PSFX_TO_SHDW_BAR2 0x8</span><br><span>@@ -51,6 +54,37 @@</span><br><span> #define PCR_DMI_LPCIOD 0x2770</span><br><span> #define PCR_DMI_LPCIOE 0x2774</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t get_pch_series(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t lpc_did;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pch_series;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_did = (pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID) & 0xFF00);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((lpc_did >> 0x8) == 0x9D)</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_series = PCH_LP;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if ((lpc_did >> 0x08) == 0xA2)</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_series = PCH_H;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_series = PCH_UNKNOWN_SERIES;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return pch_series;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint32_t get_pmc_reg_base(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t pch_series;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_series = get_pch_series();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_series == PCH_H)</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (pch_series == PCH_LP)</span><br><span style="color: hsl(120, 100%, 40%);">+ return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void soc_config_pwrmbase(void)</span><br><span> {</span><br><span> uint32_t reg32;</span><br><span>@@ -91,22 +125,27 @@</span><br><span> static void soc_config_acpibase(void)</span><br><span> {</span><br><span> uint32_t pmc_reg_value;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pmc_base_reg;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_base_reg = get_pmc_reg_base();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pmc_base_reg == 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + </span><br><span> PCR_PSFX_TO_SHDW_BAR4);</span><br><span> </span><br><span> if (pmc_reg_value != 0xFFFFFFFF)</span><br><span> {</span><br><span> /* Disable Io Space before changing the address */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_rmw32(PID_PSF3, pmc_base_reg +</span><br><span> PCR_PSFX_T0_SHDW_PCIEN,</span><br><span> ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);</span><br><span> /* Program ABASE in PSF3 PMC space BAR4*/</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_PSF3, pmc_base_reg +</span><br><span> PCR_PSFX_TO_SHDW_BAR4,</span><br><span> ACPI_BASE_ADDRESS);</span><br><span> /* Enable IO Space */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_rmw32(PID_PSF3, pmc_base_reg +</span><br><span> PCR_PSFX_T0_SHDW_PCIEN,</span><br><span> ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h</span><br><span>index 3ea9be9..74a731b 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/lpc.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/lpc.h</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #ifndef _SOC_CANNONLAKE_LPC_H_</span><br><span> #define _SOC_CANNONLAKE_LPC_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEVICE_ID 0x02</span><br><span> /* PCI Configuration Space (D31:F0): LPC */</span><br><span> #define SCI_IRQ_SEL (7 << 0)</span><br><span> #define SCIS_IRQ9 0</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27523">change 27523</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I833395260e8fb631823bd03192a092df323250fa </div>
<div style="display:none"> Gerrit-Change-Number: 27523 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>