[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use bootblock common stage
Bora Guvendik (Code Review)
gerrit at coreboot.org
Wed Jul 18 00:26:22 CEST 2018
Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/27518
Change subject: soc/intel/skylake: Use bootblock common stage
......................................................................
soc/intel/skylake: Use bootblock common stage
Change skylake bootcode to use common bootblock stage.
BUG=b:78109109
Change-Id: I46cb6bc6f6c6b97243f7d40457fd02d4ef7b8933
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/bootblock/bootblock.c
D src/soc/intel/skylake/bootblock/cpu.c
D src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/include/soc/bootblock.h
M src/soc/intel/skylake/uart.c
8 files changed, 242 insertions(+), 435 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/27518/1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 3e0158b..ac69292 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -21,6 +21,7 @@
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOTBLOCK_CONSOLE
+ select BOOTBLOCK_REPORT_PLATFORM_INFO
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
@@ -53,6 +54,8 @@
select SMP
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+ select SOC_INTEL_COMMON_BASECODE
+ select SOC_INTEL_COMMON_BASECODE_BOOTBLOCK
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index ef95cf7..57736ef 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -10,9 +10,7 @@
subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
-bootblock-y += bootblock/cpu.c
bootblock-y += i2c.c
-bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c
bootblock-y += gspi.c
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index 1803694..56bc999 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -1,7 +1,10 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corporation..
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -12,42 +15,230 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
-#include <bootblock_common.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <intelblocks/gspi.h>
+#include <arch/io.h>
+#include <chip.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <intelbasecode/bootblock.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/itss.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/rtc.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/smbus.h>
#include <soc/bootblock.h>
+#include <soc/iomap.h>
+#include <soc/p2sb.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+#include <soc/pmc.h>
+#include <soc/smbus.h>
-asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+#define PCR_DMI_DMICTL 0x2234
+#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
+#define PCR_DMI_ACPIBA 0x27B4
+#define PCR_DMI_ACPIBDID 0x27B8
+#define PCR_DMI_PMBASEA 0x27AC
+#define PCR_DMI_PMBASEC 0x27B0
+#define PCR_DMI_TCOBASE 0x2778
+
+static const struct bootblock_ops g_soc_bb_ops = {
+ &bootblock_skl_soc_early_init,
+ &bootblock_cmn_soc_init,
+ &bootblock_skl_pch_early_init,
+ &bootblock_skl_pch_init,
+ &bootblock_cmn_cpu_early_init,
+ &bootblock_cmn_cpu_init
+};
+
+
+static void enable_p2sbbar(void)
{
- /* Call lib/bootblock.c main */
- bootblock_main_with_timestamp(base_timestamp, NULL, 0);
+ pci_devfn_t dev = PCH_DEV_P2SB;
+
+ /* Enable PCR Base address in PCH */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
+
+ /* Enable P2SB MSE */
+ pci_write_config8(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ /*
+ * Enable decoding for HPET memory address range.
+ * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
+ * the High Performance Timer memory address range
+ * selected by bits 1:0
+ */
+ pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
}
-void bootblock_soc_early_init(void)
+static void soc_config_acpibase(void)
{
- bootblock_systemagent_early_init();
- bootblock_pch_early_init();
- bootblock_cpu_init();
- pch_early_iorange_init();
+ uint32_t reg32;
- if (IS_ENABLED(CONFIG_UART_DEBUG))
- pch_uart_init();
-}
+ /* Disable ABASE in PMC Device first before changing Base Address */
+ reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);
+ pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN);
-void bootblock_soc_init(void)
-{
- /* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */
- if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
- bootblock_fsp_temp_ram_init();
+ /* Program ACPI Base */
+ pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS);
+
+ /* Enable ACPI in PMC */
+ pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN);
/*
- * Perform early chipset initialization before fsp memory init
- * example: pirq->irq programming, enabling smbus, set pmcbase
- * and abase, i2c programming and print platform info
+ * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0]
+ * to [0x3F, PMC PCI Offset 40h bit[15:2], 1]
*/
- report_platform_info();
- pch_early_init();
+ reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1);
+ pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);
+ if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))
+ pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);
+ else
+ pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a0);
+}
- gspi_early_bar_init();
+static void soc_config_pwrmbase(void)
+{
+ uint32_t reg32;
+
+ /* Disable PWRMBASE in PMC Device first before changing Base address */
+ reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);
+ pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN);
+
+ /* Program PWRM Base */
+ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
+
+ /* Enable PWRM in PMC */
+ pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN);
+
+ /*
+ * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0]
+ * to the same value programmed in PMC PCI Offset 48h bit[31:16],
+ * this has an implication of making sure the PWRMBASE to be
+ * 64KB aligned.
+ *
+ * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16]
+ * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an
+ * implication of making sure the memory allocated to PWRMBASE to be
+ * 64KB in size.
+ */
+ pcr_write32(PID_DMI, PCR_DMI_PMBASEA,
+ ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |
+ (PCH_PWRM_BASE_ADDRESS >> 16)));
+ if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))
+ pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8);
+ else
+ pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0);
+}
+
+static void soc_config_tco(void)
+{
+ uint32_t reg32 = 0;
+ uint16_t tcobase;
+ uint16_t tcocnt;
+
+ /* Disable TCO in SMBUS Device first before changing Base Address */
+ reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);
+ reg32 &= ~TCO_EN;
+ pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);
+
+ /* Program TCO Base */
+ pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS);
+
+ /* Enable TCO in SMBUS */
+ pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN);
+
+ /*
+ * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
+ * to [SMBUS PCI offset 50h[15:5], 1].
+ */
+ pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1));
+
+ /* Program TCO timer halt */
+ tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
+ tcobase &= ~0x1f;
+ tcocnt = inw(tcobase + TCO1_CNT);
+ tcocnt |= TCO_TMR_HLT;
+ outw(tcocnt, tcobase + TCO1_CNT);
+}
+
+static int pch_check_decode_enable(void)
+{
+ uint32_t dmi_control;
+
+ /*
+ * This cycle decoding is only allowed to set when
+ * DMICTL.SRLOCK is 0.
+ */
+ dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
+ if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
+ return -1;
+ return 0;
+}
+
+static void pch_early_iorange_init(void)
+{
+ uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+ LPC_IOE_EC_62_66;
+
+ /* IO Decode Range */
+ if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))
+ lpc_io_setup_comm_a_b();
+
+ /* IO Decode Enable */
+ if (pch_check_decode_enable() == 0) {
+ io_enables = lpc_enable_fixed_io_ranges(io_enables);
+ /*
+ * As per PCH BWG 2.5.16.
+ * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
+ * value program in LPC PCI offset 82h.
+ */
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+ }
+
+ /* Program generic IO Decode Range */
+ pch_enable_lpc();
+}
+
+void bootblock_skl_soc_early_init(void)
+{
+ bootblock_cmn_soc_early_init();
+
+ pch_early_iorange_init();
+}
+
+void bootblock_skl_pch_early_init(void)
+{
+ bootblock_cmn_pch_early_init();
+
+ enable_p2sbbar();
+
+ /*
+ * Enabling PWRM Base for accessing
+ * Global Reset Cause Register.
+ */
+ soc_config_pwrmbase();
+}
+
+void bootblock_skl_pch_init(void)
+{
+ bootblock_cmn_pch_init();
+
+ /*
+ * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
+ * GPE0_STS, GPE0_EN registers.
+ */
+ soc_config_acpibase();
+
+ /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
+ soc_config_tco();
+}
+
+struct bootblock_ops *soc_get_ops(void)
+{
+ return (struct bootblock_ops *)&g_soc_bb_ops;
}
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
deleted file mode 100644
index 0f3038d..0000000
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <intelblocks/cpulib.h>
-#include <intelblocks/fast_spi.h>
-#include <soc/bootblock.h>
-
-void bootblock_cpu_init(void)
-{
- fast_spi_cache_bios_region();
-}
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
deleted file mode 100644
index ef61a60..0000000
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- * Copyright (C) 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <arch/io.h>
-#include <chip.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <intelblocks/cse.h>
-#include <intelblocks/fast_spi.h>
-#include <intelblocks/itss.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
-#include <intelblocks/rtc.h>
-#include <intelblocks/pmclib.h>
-#include <intelblocks/smbus.h>
-#include <soc/bootblock.h>
-#include <soc/iomap.h>
-#include <soc/p2sb.h>
-#include <soc/pch.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/pm.h>
-#include <soc/pmc.h>
-#include <soc/smbus.h>
-
-#define PCR_DMI_DMICTL 0x2234
-#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
-#define PCR_DMI_ACPIBA 0x27B4
-#define PCR_DMI_ACPIBDID 0x27B8
-#define PCR_DMI_PMBASEA 0x27AC
-#define PCR_DMI_PMBASEC 0x27B0
-#define PCR_DMI_TCOBASE 0x2778
-
-static void enable_p2sbbar(void)
-{
- pci_devfn_t dev = PCH_DEV_P2SB;
-
- /* Enable PCR Base address in PCH */
- pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
-
- /* Enable P2SB MSE */
- pci_write_config8(dev, PCI_COMMAND,
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- /*
- * Enable decoding for HPET memory address range.
- * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
- * the High Performance Timer memory address range
- * selected by bits 1:0
- */
- pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
-}
-
-void bootblock_pch_early_init(void)
-{
- fast_spi_early_init(SPI_BASE_ADDRESS);
- enable_p2sbbar();
-}
-
-static void soc_config_acpibase(void)
-{
- uint32_t reg32;
-
- /* Disable ABASE in PMC Device first before changing Base Address */
- reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);
- pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN);
-
- /* Program ACPI Base */
- pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS);
-
- /* Enable ACPI in PMC */
- pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN);
-
- /*
- * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0]
- * to [0x3F, PMC PCI Offset 40h bit[15:2], 1]
- */
- reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1);
- pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);
- if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))
- pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);
- else
- pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a0);
-}
-
-static void soc_config_pwrmbase(void)
-{
- uint32_t reg32;
-
- /* Disable PWRMBASE in PMC Device first before changing Base address */
- reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);
- pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN);
-
- /* Program PWRM Base */
- pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
-
- /* Enable PWRM in PMC */
- pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN);
-
- /*
- * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0]
- * to the same value programmed in PMC PCI Offset 48h bit[31:16],
- * this has an implication of making sure the PWRMBASE to be
- * 64KB aligned.
- *
- * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16]
- * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an
- * implication of making sure the memory allocated to PWRMBASE to be
- * 64KB in size.
- */
- pcr_write32(PID_DMI, PCR_DMI_PMBASEA,
- ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |
- (PCH_PWRM_BASE_ADDRESS >> 16)));
- if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))
- pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8);
- else
- pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0);
-}
-
-static void soc_config_tco(void)
-{
- uint32_t reg32 = 0;
- uint16_t tcobase;
- uint16_t tcocnt;
-
- /* Disable TCO in SMBUS Device first before changing Base Address */
- reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);
- reg32 &= ~TCO_EN;
- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);
-
- /* Program TCO Base */
- pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS);
-
- /* Enable TCO in SMBUS */
- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN);
-
- /*
- * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
- * to [SMBUS PCI offset 50h[15:5], 1].
- */
- pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1));
-
- /* Program TCO timer halt */
- tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
- tcobase &= ~0x1f;
- tcocnt = inw(tcobase + TCO1_CNT);
- tcocnt |= TCO_TMR_HLT;
- outw(tcocnt, tcobase + TCO1_CNT);
-}
-
-static int pch_check_decode_enable(void)
-{
- uint32_t dmi_control;
-
- /*
- * This cycle decoding is only allowed to set when
- * DMICTL.SRLOCK is 0.
- */
- dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
- if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
- return -1;
- return 0;
-}
-
-void pch_early_iorange_init(void)
-{
- uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
- LPC_IOE_EC_62_66;
-
- /* IO Decode Range */
- if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))
- lpc_io_setup_comm_a_b();
-
- /* IO Decode Enable */
- if (pch_check_decode_enable() == 0) {
- io_enables = lpc_enable_fixed_io_ranges(io_enables);
- /*
- * As per PCH BWG 2.5.16.
- * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
- * value program in LPC PCI offset 82h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
- }
-
- /* Program generic IO Decode Range */
- pch_enable_lpc();
-}
-
-void pch_early_init(void)
-{
- /*
- * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
- * GPE0_STS, GPE0_EN registers.
- */
- soc_config_acpibase();
-
- /*
- * Enabling PWRM Base for accessing
- * Global Reset Cause Register.
- */
- soc_config_pwrmbase();
-
- /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
- soc_config_tco();
-
- /* Program SMBUS_BASE_ADDRESS and Enable it */
- smbus_common_init();
-
- /* Set up GPE configuration */
- pmc_gpe_init();
-
- enable_rtc_upper_bank();
-
- /* initialize Heci interface */
- heci_init(HECI1_BASE_ADDRESS);
-}
diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c
index 8fd6599..8e3f43c 100644
--- a/src/soc/intel/skylake/bootblock/report_platform.c
+++ b/src/soc/intel/skylake/bootblock/report_platform.c
@@ -14,24 +14,14 @@
* GNU General Public License for more details.
*/
-#include <arch/cpu.h>
-#include <arch/io.h>
#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <device/pci.h>
#include <device/pci_ids.h>
+#include <intelbasecode/report_platform.h>
#include <intelblocks/mp_init.h>
#include <soc/bootblock.h>
-#include <soc/cpu.h>
-#include <soc/pch.h>
-#include <soc/pci_devs.h>
#include <soc/systemagent.h>
-#include <string.h>
-static struct {
- u32 cpuid;
- const char *name;
-} cpu_table[] = {
+static const struct cpu_info cpu_table[] = {
{ CPUID_SKYLAKE_C0, "Skylake C0" },
{ CPUID_SKYLAKE_D0, "Skylake D0" },
{ CPUID_SKYLAKE_HQ0, "Skylake H Q0" },
@@ -41,12 +31,10 @@
{ CPUID_KABYLAKE_Y0, "Kabylake Y0" },
{ CPUID_KABYLAKE_HA0, "Kabylake H A0" },
{ CPUID_KABYLAKE_HB0, "Kabylake H B0" },
+ { 0, NULL },
};
-static struct {
- u16 mchid;
- const char *name;
-} mch_table[] = {
+static const struct mch_info mch_table[] = {
{ PCI_DEVICE_ID_INTEL_SKL_ID_U, "Skylake-U" },
{ PCI_DEVICE_ID_INTEL_SKL_ID_Y, "Skylake-Y" },
{ PCI_DEVICE_ID_INTEL_SKL_ID_ULX, "Skylake-ULX" },
@@ -58,12 +46,10 @@
{ PCI_DEVICE_ID_INTEL_KBL_ID_H, "Kabylake-H" },
{ PCI_DEVICE_ID_INTEL_KBL_ID_S, "Kabylake-S" },
{ PCI_DEVICE_ID_INTEL_KBL_ID_DT, "Kabylake DT" },
+ { 0, NULL },
};
-static struct {
- u16 lpcid;
- const char *name;
-} pch_table[] = {
+static const struct pch_info pch_table[] = {
{ PCI_DEVICE_ID_INTEL_SPT_LP_SAMPLE, "Skylake LP Sample" },
{ PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE, "Skylake-U Base" },
{ PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM, "Skylake-U Premium" },
@@ -85,12 +71,10 @@
"Kabylake-U iHDCP 2.2 Premium" },
{ PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22,
"Kabylake-U iHDCP 2.2 Base" },
+ { 0, NULL },
};
-static struct {
- u16 igdid;
- const char *name;
-} igd_table[] = {
+static const struct igd_info igd_table[] = {
{ PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, "Skylake ULT GT1"},
{ PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, "Skylake ULX GT2" },
{ PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, "Skylake ULT GT2" },
@@ -102,131 +86,27 @@
{ PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, "Kabylake-R ULT GT2"},
{ PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, "Kabylake HALO GT2" },
{ PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, "Kabylake DT GT2" },
+ { 0, NULL },
};
-static uint8_t get_dev_revision(pci_devfn_t dev)
+const struct cpu_info *soc_get_cpu_id_table(void)
{
- return pci_read_config8(dev, PCI_REVISION_ID);
+ return cpu_table;
}
-static uint16_t get_dev_id(pci_devfn_t dev)
+const struct mch_info *soc_get_mch_id_table(void)
{
- return pci_read_config16(dev, PCI_DEVICE_ID);
+ return mch_table;
}
-static void report_cpu_info(void)
+const struct pch_info *soc_get_pch_id_table(void)
{
- struct cpuid_result cpuidr;
- u32 i, index;
- char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
- int vt, txt, aes;
- msr_t microcode_ver;
- static const char * const mode[] = {"NOT ", ""};
- const char *cpu_type = "Unknown";
-
- index = 0x80000000;
- cpuidr = cpuid(index);
- if (cpuidr.eax < 0x80000004) {
- strcpy(cpu_string, "Platform info not available");
- } else {
- u32 *p = (u32 *) cpu_string;
- for (i = 2; i <= 4; i++) {
- cpuidr = cpuid(index + i);
- *p++ = cpuidr.eax;
- *p++ = cpuidr.ebx;
- *p++ = cpuidr.ecx;
- *p++ = cpuidr.edx;
- }
- }
- /* Skip leading spaces in CPU name string */
- while (cpu_name[0] == ' ')
- cpu_name++;
-
- microcode_ver.lo = 0;
- microcode_ver.hi = 0;
- wrmsr(0x8B, microcode_ver);
- cpuidr = cpuid(1);
- microcode_ver = rdmsr(0x8b);
-
- /* Look for string to match the name */
- for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
- if (cpu_table[i].cpuid == cpuidr.eax) {
- cpu_type = cpu_table[i].name;
- break;
- }
- }
-
- printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
- printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
- cpuidr.eax, cpu_type, microcode_ver.hi);
-
- aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
- txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
- vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
- printk(BIOS_DEBUG,
- "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
- mode[aes], mode[txt], mode[vt]);
+ return pch_table;
}
-static void report_mch_info(void)
+const struct igd_info *soc_get_igd_id_table(void)
{
- int i;
- pci_devfn_t dev = SA_DEV_ROOT;
- uint16_t mchid = get_dev_id(dev);
- uint8_t mch_revision = get_dev_revision(dev);
- const char *mch_type = "Unknown";
-
- for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
- if (mch_table[i].mchid == mchid) {
- mch_type = mch_table[i].name;
- break;
- }
- }
-
- printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
- mchid, mch_revision, mch_type);
-}
-
-static void report_pch_info(void)
-{
- int i;
- pci_devfn_t dev = PCH_DEV_LPC;
- uint16_t lpcid = get_dev_id(dev);
- const char *pch_type = "Unknown";
-
- for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
- if (pch_table[i].lpcid == lpcid) {
- pch_type = pch_table[i].name;
- break;
- }
- }
- printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
- lpcid, get_dev_revision(dev), pch_type);
-}
-
-static void report_igd_info(void)
-{
- int i;
- pci_devfn_t dev = SA_DEV_IGD;
- uint16_t igdid = get_dev_id(dev);
- const char *igd_type = "Unknown";
-
- for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
- if (igd_table[i].igdid == igdid) {
- igd_type = igd_table[i].name;
- break;
- }
- }
- printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
- igdid, get_dev_revision(dev), igd_type);
-}
-
-void report_platform_info(void)
-{
- report_cpu_info();
- report_mch_info();
- report_pch_info();
- report_igd_info();
+ return igd_table;
}
/*
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h
index 59ce92a..432079f 100644
--- a/src/soc/intel/skylake/include/soc/bootblock.h
+++ b/src/soc/intel/skylake/include/soc/bootblock.h
@@ -16,24 +16,10 @@
#ifndef _SOC_SKYLAKE_BOOTBLOCK_H_
#define _SOC_SKYLAKE_BOOTBLOCK_H_
-#include <intelblocks/systemagent.h>
-
-#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
-#include <fsp/bootblock.h>
-#else
-static inline void bootblock_fsp_temp_ram_init(void) {}
-#endif
-
-/* Bootblock pre console init programming */
-void bootblock_cpu_init(void);
-void bootblock_pch_early_init(void);
+void bootblock_skl_soc_early_init(void);
+void bootblock_skl_pch_early_init(void);
+void bootblock_skl_pch_init(void);
void pch_uart_init(void);
-
-/* Bootblock post console init programming */
-void i2c_early_init(void);
-void pch_early_init(void);
-void pch_early_iorange_init(void);
-void report_platform_info(void);
void report_memory_config(void);
#endif
diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c
index 1b4e96e..e962b4c 100644
--- a/src/soc/intel/skylake/uart.c
+++ b/src/soc/intel/skylake/uart.c
@@ -23,6 +23,7 @@
#include <intelblocks/pcr.h>
#include <intelblocks/uart.h>
#include <soc/bootblock.h>
+#include <soc/iomap.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I46cb6bc6f6c6b97243f7d40457fd02d4ef7b8933
Gerrit-Change-Number: 27518
Gerrit-PatchSet: 1
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
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