<p>Bora Guvendik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27518">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Use bootblock common stage<br><br>Change skylake bootcode to use common bootblock stage.<br><br>BUG=b:78109109<br><br>Change-Id: I46cb6bc6f6c6b97243f7d40457fd02d4ef7b8933<br>Signed-off-by: Bora Guvendik <bora.guvendik@intel.com><br>---<br>M src/soc/intel/skylake/Kconfig<br>M src/soc/intel/skylake/Makefile.inc<br>M src/soc/intel/skylake/bootblock/bootblock.c<br>D src/soc/intel/skylake/bootblock/cpu.c<br>D src/soc/intel/skylake/bootblock/pch.c<br>M src/soc/intel/skylake/bootblock/report_platform.c<br>M src/soc/intel/skylake/include/soc/bootblock.h<br>M src/soc/intel/skylake/uart.c<br>8 files changed, 242 insertions(+), 435 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/27518/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig</span><br><span>index 3e0158b..ac69292 100644</span><br><span>--- a/src/soc/intel/skylake/Kconfig</span><br><span>+++ b/src/soc/intel/skylake/Kconfig</span><br><span>@@ -21,6 +21,7 @@</span><br><span> select ARCH_ROMSTAGE_X86_32</span><br><span> select ARCH_VERSTAGE_X86_32</span><br><span> select BOOTBLOCK_CONSOLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOOTBLOCK_REPORT_PLATFORM_INFO</span><br><span> select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH</span><br><span> select BOOT_DEVICE_SUPPORTS_WRITES</span><br><span> select CACHE_MRC_SETTINGS</span><br><span>@@ -53,6 +54,8 @@</span><br><span> select SMP</span><br><span> select SOC_INTEL_COMMON</span><br><span> select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE_BOOTBLOCK</span><br><span> select SOC_INTEL_COMMON_BLOCK</span><br><span> select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG</span><br><span> select SOC_INTEL_COMMON_BLOCK_CPU</span><br><span>diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc</span><br><span>index ef95cf7..57736ef 100644</span><br><span>--- a/src/soc/intel/skylake/Makefile.inc</span><br><span>+++ b/src/soc/intel/skylake/Makefile.inc</span><br><span>@@ -10,9 +10,7 @@</span><br><span> subdirs-y += ../../../cpu/x86/tsc</span><br><span> </span><br><span> bootblock-y += bootblock/bootblock.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += bootblock/cpu.c</span><br><span> bootblock-y += i2c.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += bootblock/pch.c</span><br><span> bootblock-y += bootblock/report_platform.c</span><br><span> bootblock-y += gpio.c</span><br><span> bootblock-y += gspi.c</span><br><span>diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c</span><br><span>index 1803694..56bc999 100644</span><br><span>--- a/src/soc/intel/skylake/bootblock/bootblock.c</span><br><span>+++ b/src/soc/intel/skylake/bootblock/bootblock.c</span><br><span>@@ -1,7 +1,10 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2016 Intel Corporation..</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -12,42 +15,230 @@</span><br><span> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <bootblock_common.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <drivers/i2c/designware/dw_i2c.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/cse.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/fast_spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/itss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/smbus.h></span><br><span> #include <soc/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/p2sb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pmc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smbus.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void bootblock_c_entry(uint64_t base_timestamp)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_DMICTL 0x2234</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_DMICTL_SRLOCK (1 << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_ACPIBA 0x27B4</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_ACPIBDID 0x27B8</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_PMBASEA 0x27AC</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_PMBASEC 0x27B0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_TCOBASE 0x2778</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct bootblock_ops g_soc_bb_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ &bootblock_skl_soc_early_init,</span><br><span style="color: hsl(120, 100%, 40%);">+ &bootblock_cmn_soc_init,</span><br><span style="color: hsl(120, 100%, 40%);">+ &bootblock_skl_pch_early_init,</span><br><span style="color: hsl(120, 100%, 40%);">+ &bootblock_skl_pch_init,</span><br><span style="color: hsl(120, 100%, 40%);">+ &bootblock_cmn_cpu_early_init,</span><br><span style="color: hsl(120, 100%, 40%);">+ &bootblock_cmn_cpu_init</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_p2sbbar(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Call lib/bootblock.c main */</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_main_with_timestamp(base_timestamp, NULL, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCH_DEV_P2SB;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable PCR Base address in PCH */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable P2SB MSE */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, PCI_COMMAND,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable decoding for HPET memory address range.</span><br><span style="color: hsl(120, 100%, 40%);">+ * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode</span><br><span style="color: hsl(120, 100%, 40%);">+ * the High Performance Timer memory address range</span><br><span style="color: hsl(120, 100%, 40%);">+ * selected by bits 1:0</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_soc_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_config_acpibase(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_systemagent_early_init();</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_pch_early_init();</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_cpu_init();</span><br><span style="color: hsl(0, 100%, 40%);">- pch_early_iorange_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_UART_DEBUG))</span><br><span style="color: hsl(0, 100%, 40%);">- pch_uart_init();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable ABASE in PMC Device first before changing Base Address */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_soc_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_fsp_temp_ram_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program ACPI Base */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable ACPI in PMC */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN);</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Perform early chipset initialization before fsp memory init</span><br><span style="color: hsl(0, 100%, 40%);">- * example: pirq->irq programming, enabling smbus, set pmcbase</span><br><span style="color: hsl(0, 100%, 40%);">- * and abase, i2c programming and print platform info</span><br><span style="color: hsl(120, 100%, 40%);">+ * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0]</span><br><span style="color: hsl(120, 100%, 40%);">+ * to [0x3F, PMC PCI Offset 40h bit[15:2], 1]</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- report_platform_info();</span><br><span style="color: hsl(0, 100%, 40%);">- pch_early_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- gspi_early_bar_init();</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_config_pwrmbase(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable PWRMBASE in PMC Device first before changing Base address */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program PWRM Base */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable PWRM in PMC */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0]</span><br><span style="color: hsl(120, 100%, 40%);">+ * to the same value programmed in PMC PCI Offset 48h bit[31:16],</span><br><span style="color: hsl(120, 100%, 40%);">+ * this has an implication of making sure the PWRMBASE to be</span><br><span style="color: hsl(120, 100%, 40%);">+ * 64KB aligned.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16]</span><br><span style="color: hsl(120, 100%, 40%);">+ * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an</span><br><span style="color: hsl(120, 100%, 40%);">+ * implication of making sure the memory allocated to PWRMBASE to be</span><br><span style="color: hsl(120, 100%, 40%);">+ * 64KB in size.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_PMBASEA,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (PCH_PWRM_BASE_ADDRESS >> 16)));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_config_tco(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tcobase;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tcocnt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable TCO in SMBUS Device first before changing Base Address */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~TCO_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program TCO Base */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable TCO in SMBUS */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ * to [SMBUS PCI offset 50h[15:5], 1].</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program TCO timer halt */</span><br><span style="color: hsl(120, 100%, 40%);">+ tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);</span><br><span style="color: hsl(120, 100%, 40%);">+ tcobase &= ~0x1f;</span><br><span style="color: hsl(120, 100%, 40%);">+ tcocnt = inw(tcobase + TCO1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ tcocnt |= TCO_TMR_HLT;</span><br><span style="color: hsl(120, 100%, 40%);">+ outw(tcocnt, tcobase + TCO1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int pch_check_decode_enable(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dmi_control;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This cycle decoding is only allowed to set when</span><br><span style="color: hsl(120, 100%, 40%);">+ * DMICTL.SRLOCK is 0.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dmi_control & PCR_DMI_DMICTL_SRLOCK)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_early_iorange_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |</span><br><span style="color: hsl(120, 100%, 40%);">+ LPC_IOE_EC_62_66;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IO Decode Range */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_io_setup_comm_a_b();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IO Decode Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_check_decode_enable() == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ io_enables = lpc_enable_fixed_io_ranges(io_enables);</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * As per PCH BWG 2.5.16.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same</span><br><span style="color: hsl(120, 100%, 40%);">+ * value program in LPC PCI offset 82h.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program generic IO Decode Range */</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_enable_lpc();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_skl_soc_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_cmn_soc_early_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_early_iorange_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_skl_pch_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_cmn_pch_early_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_p2sbbar();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enabling PWRM Base for accessing</span><br><span style="color: hsl(120, 100%, 40%);">+ * Global Reset Cause Register.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_config_pwrmbase();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_skl_pch_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_cmn_pch_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,</span><br><span style="color: hsl(120, 100%, 40%);">+ * GPE0_STS, GPE0_EN registers.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_config_acpibase();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_config_tco();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct bootblock_ops *soc_get_ops(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return (struct bootblock_ops *)&g_soc_bb_ops;</span><br><span> }</span><br><span>diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c</span><br><span>deleted file mode 100644</span><br><span>index 0f3038d..0000000</span><br><span>--- a/src/soc/intel/skylake/bootblock/cpu.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,24 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/cpulib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/fast_spi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/bootblock.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_cpu_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_cache_bios_region();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c</span><br><span>deleted file mode 100644</span><br><span>index ef61a60..0000000</span><br><span>--- a/src/soc/intel/skylake/bootblock/pch.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,228 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2016 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <chip.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_def.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/cse.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/fast_spi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/itss.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/pcr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/rtc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/pmclib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/smbus.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/bootblock.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/iomap.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/p2sb.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pcr_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pmc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/smbus.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_DMICTL 0x2234</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_DMICTL_SRLOCK (1 << 31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_ACPIBA 0x27B4</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_ACPIBDID 0x27B8</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_PMBASEA 0x27AC</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_PMBASEC 0x27B0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_TCOBASE 0x2778</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_p2sbbar(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- pci_devfn_t dev = PCH_DEV_P2SB;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable PCR Base address in PCH */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable P2SB MSE */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, PCI_COMMAND,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Enable decoding for HPET memory address range.</span><br><span style="color: hsl(0, 100%, 40%);">- * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode</span><br><span style="color: hsl(0, 100%, 40%);">- * the High Performance Timer memory address range</span><br><span style="color: hsl(0, 100%, 40%);">- * selected by bits 1:0</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_pch_early_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_early_init(SPI_BASE_ADDRESS);</span><br><span style="color: hsl(0, 100%, 40%);">- enable_p2sbbar();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_config_acpibase(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable ABASE in PMC Device first before changing Base Address */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Program ACPI Base */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable ACPI in PMC */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0]</span><br><span style="color: hsl(0, 100%, 40%);">- * to [0x3F, PMC PCI Offset 40h bit[15:2], 1]</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1);</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a0);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_config_pwrmbase(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable PWRMBASE in PMC Device first before changing Base address */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Program PWRM Base */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable PWRM in PMC */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0]</span><br><span style="color: hsl(0, 100%, 40%);">- * to the same value programmed in PMC PCI Offset 48h bit[31:16],</span><br><span style="color: hsl(0, 100%, 40%);">- * this has an implication of making sure the PWRMBASE to be</span><br><span style="color: hsl(0, 100%, 40%);">- * 64KB aligned.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16]</span><br><span style="color: hsl(0, 100%, 40%);">- * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an</span><br><span style="color: hsl(0, 100%, 40%);">- * implication of making sure the memory allocated to PWRMBASE to be</span><br><span style="color: hsl(0, 100%, 40%);">- * 64KB in size.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_PMBASEA,</span><br><span style="color: hsl(0, 100%, 40%);">- ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |</span><br><span style="color: hsl(0, 100%, 40%);">- (PCH_PWRM_BASE_ADDRESS >> 16)));</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8);</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_config_tco(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t reg32 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t tcobase;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t tcocnt;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable TCO in SMBUS Device first before changing Base Address */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= ~TCO_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Program TCO Base */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable TCO in SMBUS */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]</span><br><span style="color: hsl(0, 100%, 40%);">- * to [SMBUS PCI offset 50h[15:5], 1].</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Program TCO timer halt */</span><br><span style="color: hsl(0, 100%, 40%);">- tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);</span><br><span style="color: hsl(0, 100%, 40%);">- tcobase &= ~0x1f;</span><br><span style="color: hsl(0, 100%, 40%);">- tcocnt = inw(tcobase + TCO1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- tcocnt |= TCO_TMR_HLT;</span><br><span style="color: hsl(0, 100%, 40%);">- outw(tcocnt, tcobase + TCO1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int pch_check_decode_enable(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t dmi_control;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * This cycle decoding is only allowed to set when</span><br><span style="color: hsl(0, 100%, 40%);">- * DMICTL.SRLOCK is 0.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);</span><br><span style="color: hsl(0, 100%, 40%);">- if (dmi_control & PCR_DMI_DMICTL_SRLOCK)</span><br><span style="color: hsl(0, 100%, 40%);">- return -1;</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_early_iorange_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |</span><br><span style="color: hsl(0, 100%, 40%);">- LPC_IOE_EC_62_66;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* IO Decode Range */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_io_setup_comm_a_b();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* IO Decode Enable */</span><br><span style="color: hsl(0, 100%, 40%);">- if (pch_check_decode_enable() == 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- io_enables = lpc_enable_fixed_io_ranges(io_enables);</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * As per PCH BWG 2.5.16.</span><br><span style="color: hsl(0, 100%, 40%);">- * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same</span><br><span style="color: hsl(0, 100%, 40%);">- * value program in LPC PCI offset 82h.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Program generic IO Decode Range */</span><br><span style="color: hsl(0, 100%, 40%);">- pch_enable_lpc();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_early_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,</span><br><span style="color: hsl(0, 100%, 40%);">- * GPE0_STS, GPE0_EN registers.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- soc_config_acpibase();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Enabling PWRM Base for accessing</span><br><span style="color: hsl(0, 100%, 40%);">- * Global Reset Cause Register.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- soc_config_pwrmbase();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */</span><br><span style="color: hsl(0, 100%, 40%);">- soc_config_tco();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Program SMBUS_BASE_ADDRESS and Enable it */</span><br><span style="color: hsl(0, 100%, 40%);">- smbus_common_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set up GPE configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- pmc_gpe_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- enable_rtc_upper_bank();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* initialize Heci interface */</span><br><span style="color: hsl(0, 100%, 40%);">- heci_init(HECI1_BASE_ADDRESS);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c</span><br><span>index 8fd6599..8e3f43c 100644</span><br><span>--- a/src/soc/intel/skylake/bootblock/report_platform.c</span><br><span>+++ b/src/soc/intel/skylake/bootblock/report_platform.c</span><br><span>@@ -14,24 +14,14 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/cpu.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/report_platform.h></span><br><span> #include <intelblocks/mp_init.h></span><br><span> #include <soc/bootblock.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/cpu.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pci_devs.h></span><br><span> #include <soc/systemagent.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 cpuid;</span><br><span style="color: hsl(0, 100%, 40%);">- const char *name;</span><br><span style="color: hsl(0, 100%, 40%);">-} cpu_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct cpu_info cpu_table[] = {</span><br><span> { CPUID_SKYLAKE_C0, "Skylake C0" },</span><br><span> { CPUID_SKYLAKE_D0, "Skylake D0" },</span><br><span> { CPUID_SKYLAKE_HQ0, "Skylake H Q0" },</span><br><span>@@ -41,12 +31,10 @@</span><br><span> { CPUID_KABYLAKE_Y0, "Kabylake Y0" },</span><br><span> { CPUID_KABYLAKE_HA0, "Kabylake H A0" },</span><br><span> { CPUID_KABYLAKE_HB0, "Kabylake H B0" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, NULL },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u16 mchid;</span><br><span style="color: hsl(0, 100%, 40%);">- const char *name;</span><br><span style="color: hsl(0, 100%, 40%);">-} mch_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct mch_info mch_table[] = {</span><br><span> { PCI_DEVICE_ID_INTEL_SKL_ID_U, "Skylake-U" },</span><br><span> { PCI_DEVICE_ID_INTEL_SKL_ID_Y, "Skylake-Y" },</span><br><span> { PCI_DEVICE_ID_INTEL_SKL_ID_ULX, "Skylake-ULX" },</span><br><span>@@ -58,12 +46,10 @@</span><br><span> { PCI_DEVICE_ID_INTEL_KBL_ID_H, "Kabylake-H" },</span><br><span> { PCI_DEVICE_ID_INTEL_KBL_ID_S, "Kabylake-S" },</span><br><span> { PCI_DEVICE_ID_INTEL_KBL_ID_DT, "Kabylake DT" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, NULL },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u16 lpcid;</span><br><span style="color: hsl(0, 100%, 40%);">- const char *name;</span><br><span style="color: hsl(0, 100%, 40%);">-} pch_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_info pch_table[] = {</span><br><span> { PCI_DEVICE_ID_INTEL_SPT_LP_SAMPLE, "Skylake LP Sample" },</span><br><span> { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE, "Skylake-U Base" },</span><br><span> { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM, "Skylake-U Premium" },</span><br><span>@@ -85,12 +71,10 @@</span><br><span> "Kabylake-U iHDCP 2.2 Premium" },</span><br><span> { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22,</span><br><span> "Kabylake-U iHDCP 2.2 Base" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, NULL },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u16 igdid;</span><br><span style="color: hsl(0, 100%, 40%);">- const char *name;</span><br><span style="color: hsl(0, 100%, 40%);">-} igd_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct igd_info igd_table[] = {</span><br><span> { PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, "Skylake ULT GT1"},</span><br><span> { PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, "Skylake ULX GT2" },</span><br><span> { PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, "Skylake ULT GT2" },</span><br><span>@@ -102,131 +86,27 @@</span><br><span> { PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, "Kabylake-R ULT GT2"},</span><br><span> { PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, "Kabylake HALO GT2" },</span><br><span> { PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, "Kabylake DT GT2" },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, NULL },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static uint8_t get_dev_revision(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cpu_info *soc_get_cpu_id_table(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return pci_read_config8(dev, PCI_REVISION_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ return cpu_table;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static uint16_t get_dev_id(pci_devfn_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct mch_info *soc_get_mch_id_table(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return pci_read_config16(dev, PCI_DEVICE_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ return mch_table;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void report_cpu_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_info *soc_get_pch_id_table(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- struct cpuid_result cpuidr;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 i, index;</span><br><span style="color: hsl(0, 100%, 40%);">- char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */</span><br><span style="color: hsl(0, 100%, 40%);">- int vt, txt, aes;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t microcode_ver;</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const mode[] = {"NOT ", ""};</span><br><span style="color: hsl(0, 100%, 40%);">- const char *cpu_type = "Unknown";</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- index = 0x80000000;</span><br><span style="color: hsl(0, 100%, 40%);">- cpuidr = cpuid(index);</span><br><span style="color: hsl(0, 100%, 40%);">- if (cpuidr.eax < 0x80000004) {</span><br><span style="color: hsl(0, 100%, 40%);">- strcpy(cpu_string, "Platform info not available");</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 *p = (u32 *) cpu_string;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 2; i <= 4; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- cpuidr = cpuid(index + i);</span><br><span style="color: hsl(0, 100%, 40%);">- *p++ = cpuidr.eax;</span><br><span style="color: hsl(0, 100%, 40%);">- *p++ = cpuidr.ebx;</span><br><span style="color: hsl(0, 100%, 40%);">- *p++ = cpuidr.ecx;</span><br><span style="color: hsl(0, 100%, 40%);">- *p++ = cpuidr.edx;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- /* Skip leading spaces in CPU name string */</span><br><span style="color: hsl(0, 100%, 40%);">- while (cpu_name[0] == ' ')</span><br><span style="color: hsl(0, 100%, 40%);">- cpu_name++;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- microcode_ver.lo = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- microcode_ver.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0x8B, microcode_ver);</span><br><span style="color: hsl(0, 100%, 40%);">- cpuidr = cpuid(1);</span><br><span style="color: hsl(0, 100%, 40%);">- microcode_ver = rdmsr(0x8b);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Look for string to match the name */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (cpu_table[i].cpuid == cpuidr.eax) {</span><br><span style="color: hsl(0, 100%, 40%);">- cpu_type = cpu_table[i].name;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- cpuidr.eax, cpu_type, microcode_ver.hi);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;</span><br><span style="color: hsl(0, 100%, 40%);">- txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;</span><br><span style="color: hsl(0, 100%, 40%);">- vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG,</span><br><span style="color: hsl(0, 100%, 40%);">- "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",</span><br><span style="color: hsl(0, 100%, 40%);">- mode[aes], mode[txt], mode[vt]);</span><br><span style="color: hsl(120, 100%, 40%);">+ return pch_table;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void report_mch_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct igd_info *soc_get_igd_id_table(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_devfn_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t mchid = get_dev_id(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t mch_revision = get_dev_revision(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- const char *mch_type = "Unknown";</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(mch_table); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (mch_table[i].mchid == mchid) {</span><br><span style="color: hsl(0, 100%, 40%);">- mch_type = mch_table[i].name;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",</span><br><span style="color: hsl(0, 100%, 40%);">- mchid, mch_revision, mch_type);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void report_pch_info(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_devfn_t dev = PCH_DEV_LPC;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t lpcid = get_dev_id(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- const char *pch_type = "Unknown";</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(pch_table); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (pch_table[i].lpcid == lpcid) {</span><br><span style="color: hsl(0, 100%, 40%);">- pch_type = pch_table[i].name;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",</span><br><span style="color: hsl(0, 100%, 40%);">- lpcid, get_dev_revision(dev), pch_type);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void report_igd_info(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_devfn_t dev = SA_DEV_IGD;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t igdid = get_dev_id(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- const char *igd_type = "Unknown";</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(igd_table); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (igd_table[i].igdid == igdid) {</span><br><span style="color: hsl(0, 100%, 40%);">- igd_type = igd_table[i].name;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",</span><br><span style="color: hsl(0, 100%, 40%);">- igdid, get_dev_revision(dev), igd_type);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void report_platform_info(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- report_cpu_info();</span><br><span style="color: hsl(0, 100%, 40%);">- report_mch_info();</span><br><span style="color: hsl(0, 100%, 40%);">- report_pch_info();</span><br><span style="color: hsl(0, 100%, 40%);">- report_igd_info();</span><br><span style="color: hsl(120, 100%, 40%);">+ return igd_table;</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h</span><br><span>index 59ce92a..432079f 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/bootblock.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/bootblock.h</span><br><span>@@ -16,24 +16,10 @@</span><br><span> #ifndef _SOC_SKYLAKE_BOOTBLOCK_H_</span><br><span> #define _SOC_SKYLAKE_BOOTBLOCK_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/systemagent.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)</span><br><span style="color: hsl(0, 100%, 40%);">-#include <fsp/bootblock.h></span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-static inline void bootblock_fsp_temp_ram_init(void) {}</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Bootblock pre console init programming */</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_cpu_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_pch_early_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_skl_soc_early_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_skl_pch_early_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_skl_pch_init(void);</span><br><span> void pch_uart_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Bootblock post console init programming */</span><br><span style="color: hsl(0, 100%, 40%);">-void i2c_early_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_early_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_early_iorange_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void report_platform_info(void);</span><br><span> void report_memory_config(void);</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c</span><br><span>index 1b4e96e..e962b4c 100644</span><br><span>--- a/src/soc/intel/skylake/uart.c</span><br><span>+++ b/src/soc/intel/skylake/uart.c</span><br><span>@@ -23,6 +23,7 @@</span><br><span> #include <intelblocks/pcr.h></span><br><span> #include <intelblocks/uart.h></span><br><span> #include <soc/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span> #include <soc/nvs.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pcr_ids.h></span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27518">change 27518</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I46cb6bc6f6c6b97243f7d40457fd02d4ef7b8933 </div>
<div style="display:none"> Gerrit-Change-Number: 27518 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Bora Guvendik <bora.guvendik@intel.com> </div>