[coreboot-gerrit] Change in coreboot[master]: libpayload/xhci: Document struct offsets on xhci_t
Raul Rangel (Code Review)
gerrit at coreboot.org
Fri Jul 13 23:17:03 CEST 2018
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27474
Change subject: libpayload/xhci: Document struct offsets on xhci_t
......................................................................
libpayload/xhci: Document struct offsets on xhci_t
This makes it easier to know what offset each register references.
BUG=b:76831439
TEST=none
Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6
Signed-off-by: Raul E Rangel <rrangel at chromium.org>
---
M payloads/libpayload/drivers/usb/xhci_private.h
1 file changed, 25 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27474/1
diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h
index 14d0e89..ab1dfa9 100644
--- a/payloads/libpayload/drivers/usb/xhci_private.h
+++ b/payloads/libpayload/drivers/usb/xhci_private.h
@@ -325,16 +325,16 @@
/* capreg is read-only, so no need for volatile,
and thus 32bit accesses can be assumed. */
struct capreg {
- u8 caplength;
- u8 res1;
- union {
+ u8 caplength; /* 0x00 */
+ u8 res1; /* 0x01 */
+ union { /* 0x02 */
u16 hciversion;
struct {
u8 hciver_lo;
u8 hciver_hi;
} __packed;
} __packed;
- union {
+ union { /* 0x04 */
u32 hcsparams1;
struct {
unsigned long MaxSlots:7;
@@ -343,7 +343,7 @@
unsigned long MaxPorts:8;
} __packed;
} __packed;
- union {
+ union { /* 0x08 */
u32 hcsparams2;
struct {
unsigned long IST:4;
@@ -354,7 +354,7 @@
unsigned long Max_Scratchpad_Bufs_Lo:5;
} __packed;
} __packed;
- union {
+ union { /* 0x0C */
u32 hcsparams3;
struct {
unsigned long u1latency:8;
@@ -362,7 +362,7 @@
unsigned long u2latency:16;
} __packed;
} __packed;
- union {
+ union { /* 0x10 */
u32 hccparams;
struct {
unsigned long ac64:1;
@@ -378,42 +378,42 @@
unsigned long xECP:16;
} __packed;
} __packed;
- u32 dboff;
- u32 rtsoff;
+ u32 dboff; /* 0x14 */
+ u32 rtsoff; /* 0x18 */
} __packed *capreg;
/* opreg is R/W is most places, so volatile access is necessary.
volatile means that the compiler seeks byte writes if possible,
making bitfields unusable for MMIO register blocks. Yay C :-( */
volatile struct opreg {
- u32 usbcmd;
+ u32 usbcmd; /* 0x00 */
#define USBCMD_RS (1 << 0)
#define USBCMD_HCRST (1 << 1)
#define USBCMD_INTE (1 << 2)
- u32 usbsts;
+ u32 usbsts; /* 0x04 */
#define USBSTS_HCH (1 << 0)
#define USBSTS_HSE (1 << 2)
#define USBSTS_EINT (1 << 3)
#define USBSTS_PCD (1 << 4)
#define USBSTS_CNR (1 << 11)
#define USBSTS_PRSRV_MASK ((1 << 1) | 0xffffe000)
- u32 pagesize;
- u8 res1[0x13-0x0c+1];
- u32 dnctrl;
- u32 crcr_lo;
- u32 crcr_hi;
+ u32 pagesize; /* 0x08 */
+ u8 res1[0x13-0x0c+1]; /* 0x0C */
+ u32 dnctrl; /* 0x14 */
+ u32 crcr_lo; /* 0x18 */
+ u32 crcr_hi; /* 0x1C */
#define CRCR_RCS (1 << 0)
#define CRCR_CS (1 << 1)
#define CRCR_CA (1 << 2)
#define CRCR_CRR (1 << 3)
- u8 res2[0x2f-0x20+1];
- u32 dcbaap_lo;
- u32 dcbaap_hi;
- u32 config;
+ u8 res2[0x2f-0x20+1]; /* 0x20 */
+ u32 dcbaap_lo; /* 0x30 */
+ u32 dcbaap_hi; /* 0x34 */
+ u32 config; /* 0x38 */
#define CONFIG_LP_MASK_MaxSlotsEn 0xff
- u8 res3[0x3ff-0x3c+1];
+ u8 res3[0x3ff-0x3c+1]; /* 0x3C */
struct {
- u32 portsc;
+ u32 portsc; /* 0x400 + 4 * port */
#define PORTSC_CCS (1 << 0)
#define PORTSC_PED (1 << 1)
// BIT 2 rsvdZ
@@ -443,9 +443,9 @@
#define PORTSC_DR (1 << 30)
#define PORTSC_WPR (1 << 31)
#define PORTSC_RW_MASK (PORTSC_PR | PORTSC_PLS_MASK | PORTSC_PP | PORTSC_PIC_MASK | PORTSC_LWS | PORTSC_WCE | PORTSC_WDE | PORTSC_WOE)
- u32 portpmsc;
- u32 portli;
- u32 res;
+ u32 portpmsc; /* 0x404 + 4 * port */
+ u32 portli; /* 0x408 + 4 * port */
+ u32 res; /* 0x40C + 4 * port */
} __packed prs[];
} __packed *opreg;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6
Gerrit-Change-Number: 27474
Gerrit-PatchSet: 1
Gerrit-Owner: Raul Rangel <rrangel at chromium.org>
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