[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell/ramstage.c: SoC D-1 revision reported as stepping ??.

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27471 )

Change subject: soc/intel/braswell/ramstage.c: SoC D-1 revision reported as stepping ??.
......................................................................


Patch Set 1:

(4 comments)

https://review.coreboot.org/#/c/27471/1/src/soc/intel/braswell/ramstage.c
File src/soc/intel/braswell/ramstage.c:

https://review.coreboot.org/#/c/27471/1/src/soc/intel/braswell/ramstage.c@90
PS1, Line 90:     if (attrs->revid >= RID_D_STEPPING_START) {
please, no spaces at the start of a line


https://review.coreboot.org/#/c/27471/1/src/soc/intel/braswell/ramstage.c@90
PS1, Line 90:     if (attrs->revid >= RID_D_STEPPING_START) {
suspect code indent for conditional statements (4, 16)


https://review.coreboot.org/#/c/27471/1/src/soc/intel/braswell/ramstage.c@93
PS1, Line 93:     } else if (attrs->revid >= RID_C_STEPPING_START) {
please, no spaces at the start of a line


https://review.coreboot.org/#/c/27471/1/src/soc/intel/braswell/ramstage.c@93
PS1, Line 93:     } else if (attrs->revid >= RID_C_STEPPING_START) {
suspect code indent for conditional statements (4, 16)



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4
Gerrit-Change-Number: 27471
Gerrit-PatchSet: 1
Gerrit-Owner: Frans Hendriks <fhendriks at eltan.com>
Gerrit-CC: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Fri, 13 Jul 2018 07:54:00 +0000
Gerrit-HasComments: Yes
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