[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell/ramstage.c: SoC D-1 revision reported as stepping ??.

[Frans Hendriks (Code Review)]

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/27471


Change subject: soc/intel/braswell/ramstage.c: SoC D-1 revision reported as stepping ??.
......................................................................

soc/intel/braswell/ramstage.c: SoC D-1 revision reported as stepping ??.

No support for SoC D-1 stepping is available.

According to Intel doc #332095-015 stepping C-0 has revision
id 0x21 and D-1 revision ID 0x35.

Also correct the RID_C_STEPPING_START value for C-0.

BUG=none
TEST=Built, Intel Cherry Hill Rev F.

Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4
Signed-off-by: Frans Hendriks <fhendriks at eltan.com>
---
M src/soc/intel/braswell/include/soc/lpc.h
M src/soc/intel/braswell/ramstage.c
2 files changed, 10 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27471/1

diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h
index d842274..7b1e3424 100644
--- a/src/soc/intel/braswell/include/soc/lpc.h
+++ b/src/soc/intel/braswell/include/soc/lpc.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -36,7 +37,8 @@
 
 #define RID_A_STEPPING_START 1
 #define RID_B_STEPPING_START 5
-#define RID_C_STEPPING_START 0xe
+#define RID_C_STEPPING_START 0x21
+#define RID_D_STEPPING_START 0x35
 enum soc_stepping {
 	STEP_A0,
 	STEP_A1,
@@ -45,6 +47,7 @@
 	STEP_B2,
 	STEP_B3,
 	STEP_C0,
+	STEP_D1,
 };
 
 /* Registers behind the RCBA_BASE_ADDRESS bar. */
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 4559739..20c09d5 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -73,7 +74,7 @@
 }
 
 static const char *const stepping_str[] = {
-	"A0", "A1", "B0", "B1", "B2", "B3", "C0"
+	"A0", "A1", "B0", "B1", "B2", "B3", "C0", "D1"
 };
 
 static void fill_in_pattrs(void)
@@ -86,7 +87,10 @@
 	dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
 	attrs->revid = pci_read_config8(dev, REVID);
 	/* The revision to stepping IDs have two values per metal stepping. */
-	if (attrs->revid >= RID_C_STEPPING_START) {
+    if (attrs->revid >= RID_D_STEPPING_START) {
+		attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2;
+		attrs->stepping += STEP_D1;
+    } else if (attrs->revid >= RID_C_STEPPING_START) {
 		attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2;
 		attrs->stepping += STEP_C0;
 	} else if (attrs->revid >= RID_B_STEPPING_START) {

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4
Gerrit-Change-Number: 27471
Gerrit-PatchSet: 1
Gerrit-Owner: Frans Hendriks <fhendriks at eltan.com>
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