<p>Frans Hendriks has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27471">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/braswell/ramstage.c: SoC D-1 revision reported as stepping ??.<br><br>No support for SoC D-1 stepping is available.<br><br>According to Intel doc #332095-015 stepping C-0 has revision<br>id 0x21 and D-1 revision ID 0x35.<br><br>Also correct the RID_C_STEPPING_START value for C-0.<br><br>BUG=none<br>TEST=Built, Intel Cherry Hill Rev F.<br><br>Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4<br>Signed-off-by: Frans Hendriks <fhendriks@eltan.com><br>---<br>M src/soc/intel/braswell/include/soc/lpc.h<br>M src/soc/intel/braswell/ramstage.c<br>2 files changed, 10 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27471/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h</span><br><span>index d842274..7b1e3424 100644</span><br><span>--- a/src/soc/intel/braswell/include/soc/lpc.h</span><br><span>+++ b/src/soc/intel/braswell/include/soc/lpc.h</span><br><span>@@ -3,6 +3,7 @@</span><br><span>  *</span><br><span>  * Copyright (C) 2013 Google Inc.</span><br><span>  * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Eltan B.V.</span><br><span>  *</span><br><span>  * This program is free software; you can redistribute it and/or modify</span><br><span>  * it under the terms of the GNU General Public License as published by</span><br><span>@@ -36,7 +37,8 @@</span><br><span> </span><br><span> #define RID_A_STEPPING_START 1</span><br><span> #define RID_B_STEPPING_START 5</span><br><span style="color: hsl(0, 100%, 40%);">-#define RID_C_STEPPING_START 0xe</span><br><span style="color: hsl(120, 100%, 40%);">+#define RID_C_STEPPING_START 0x21</span><br><span style="color: hsl(120, 100%, 40%);">+#define RID_D_STEPPING_START 0x35</span><br><span> enum soc_stepping {</span><br><span>     STEP_A0,</span><br><span>     STEP_A1,</span><br><span>@@ -45,6 +47,7 @@</span><br><span>         STEP_B2,</span><br><span>     STEP_B3,</span><br><span>     STEP_C0,</span><br><span style="color: hsl(120, 100%, 40%);">+      STEP_D1,</span><br><span> };</span><br><span> </span><br><span> /* Registers behind the RCBA_BASE_ADDRESS bar. */</span><br><span>diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c</span><br><span>index 4559739..20c09d5 100644</span><br><span>--- a/src/soc/intel/braswell/ramstage.c</span><br><span>+++ b/src/soc/intel/braswell/ramstage.c</span><br><span>@@ -3,6 +3,7 @@</span><br><span>  *</span><br><span>  * Copyright (C) 2013 Google Inc.</span><br><span>  * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Eltan B.V.</span><br><span>  *</span><br><span>  * This program is free software; you can redistribute it and/or modify</span><br><span>  * it under the terms of the GNU General Public License as published by</span><br><span>@@ -73,7 +74,7 @@</span><br><span> }</span><br><span> </span><br><span> static const char *const stepping_str[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-    "A0", "A1", "B0", "B1", "B2", "B3", "C0"</span><br><span style="color: hsl(120, 100%, 40%);">+        "A0", "A1", "B0", "B1", "B2", "B3", "C0", "D1"</span><br><span> };</span><br><span> </span><br><span> static void fill_in_pattrs(void)</span><br><span>@@ -86,7 +87,10 @@</span><br><span>    dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));</span><br><span>        attrs->revid = pci_read_config8(dev, REVID);</span><br><span>      /* The revision to stepping IDs have two values per metal stepping. */</span><br><span style="color: hsl(0, 100%, 40%);">-  if (attrs->revid >= RID_C_STEPPING_START) {</span><br><span style="color: hsl(120, 100%, 40%);">+    if (attrs->revid >= RID_D_STEPPING_START) {</span><br><span style="color: hsl(120, 100%, 40%);">+              attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2;</span><br><span style="color: hsl(120, 100%, 40%);">+            attrs->stepping += STEP_D1;</span><br><span style="color: hsl(120, 100%, 40%);">+    } else if (attrs->revid >= RID_C_STEPPING_START) {</span><br><span>                 attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2;</span><br><span>           attrs->stepping += STEP_C0;</span><br><span>       } else if (attrs->revid >= RID_B_STEPPING_START) {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27471">change 27471</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><d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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4 </div>
<div style="display:none"> Gerrit-Change-Number: 27471 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Frans Hendriks <fhendriks@eltan.com> </div>