<p>Raul Rangel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27474">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">libpayload/xhci: Document struct offsets on xhci_t<br><br>This makes it easier to know what offset each register references.<br><br>BUG=b:76831439<br>TEST=none<br><br>Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6<br>Signed-off-by: Raul E Rangel <rrangel@chromium.org><br>---<br>M payloads/libpayload/drivers/usb/xhci_private.h<br>1 file changed, 25 insertions(+), 25 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27474/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h</span><br><span>index 14d0e89..ab1dfa9 100644</span><br><span>--- a/payloads/libpayload/drivers/usb/xhci_private.h</span><br><span>+++ b/payloads/libpayload/drivers/usb/xhci_private.h</span><br><span>@@ -325,16 +325,16 @@</span><br><span> /* capreg is read-only, so no need for volatile,</span><br><span> and thus 32bit accesses can be assumed. */</span><br><span> struct capreg {</span><br><span style="color: hsl(0, 100%, 40%);">- u8 caplength;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 res1;</span><br><span style="color: hsl(0, 100%, 40%);">- union {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 caplength; /* 0x00 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 res1; /* 0x01 */</span><br><span style="color: hsl(120, 100%, 40%);">+ union { /* 0x02 */</span><br><span> u16 hciversion;</span><br><span> struct {</span><br><span> u8 hciver_lo;</span><br><span> u8 hciver_hi;</span><br><span> } __packed;</span><br><span> } __packed;</span><br><span style="color: hsl(0, 100%, 40%);">- union {</span><br><span style="color: hsl(120, 100%, 40%);">+ union { /* 0x04 */</span><br><span> u32 hcsparams1;</span><br><span> struct {</span><br><span> unsigned long MaxSlots:7;</span><br><span>@@ -343,7 +343,7 @@</span><br><span> unsigned long MaxPorts:8;</span><br><span> } __packed;</span><br><span> } __packed;</span><br><span style="color: hsl(0, 100%, 40%);">- union {</span><br><span style="color: hsl(120, 100%, 40%);">+ union { /* 0x08 */</span><br><span> u32 hcsparams2;</span><br><span> struct {</span><br><span> unsigned long IST:4;</span><br><span>@@ -354,7 +354,7 @@</span><br><span> unsigned long Max_Scratchpad_Bufs_Lo:5;</span><br><span> } __packed;</span><br><span> } __packed;</span><br><span style="color: hsl(0, 100%, 40%);">- union {</span><br><span style="color: hsl(120, 100%, 40%);">+ union { /* 0x0C */</span><br><span> u32 hcsparams3;</span><br><span> struct {</span><br><span> unsigned long u1latency:8;</span><br><span>@@ -362,7 +362,7 @@</span><br><span> unsigned long u2latency:16;</span><br><span> } __packed;</span><br><span> } __packed;</span><br><span style="color: hsl(0, 100%, 40%);">- union {</span><br><span style="color: hsl(120, 100%, 40%);">+ union { /* 0x10 */</span><br><span> u32 hccparams;</span><br><span> struct {</span><br><span> unsigned long ac64:1;</span><br><span>@@ -378,42 +378,42 @@</span><br><span> unsigned long xECP:16;</span><br><span> } __packed;</span><br><span> } __packed;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 dboff;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 rtsoff;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dboff; /* 0x14 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rtsoff; /* 0x18 */</span><br><span> } __packed *capreg;</span><br><span> </span><br><span> /* opreg is R/W is most places, so volatile access is necessary.</span><br><span> volatile means that the compiler seeks byte writes if possible,</span><br><span> making bitfields unusable for MMIO register blocks. Yay C :-( */</span><br><span> volatile struct opreg {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 usbcmd;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 usbcmd; /* 0x00 */</span><br><span> #define USBCMD_RS (1 << 0)</span><br><span> #define USBCMD_HCRST (1 << 1)</span><br><span> #define USBCMD_INTE (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">- u32 usbsts;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 usbsts; /* 0x04 */</span><br><span> #define USBSTS_HCH (1 << 0)</span><br><span> #define USBSTS_HSE (1 << 2)</span><br><span> #define USBSTS_EINT (1 << 3)</span><br><span> #define USBSTS_PCD (1 << 4)</span><br><span> #define USBSTS_CNR (1 << 11)</span><br><span> #define USBSTS_PRSRV_MASK ((1 << 1) | 0xffffe000)</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pagesize;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 res1[0x13-0x0c+1];</span><br><span style="color: hsl(0, 100%, 40%);">- u32 dnctrl;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 crcr_lo;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 crcr_hi;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pagesize; /* 0x08 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 res1[0x13-0x0c+1]; /* 0x0C */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dnctrl; /* 0x14 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 crcr_lo; /* 0x18 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 crcr_hi; /* 0x1C */</span><br><span> #define CRCR_RCS (1 << 0)</span><br><span> #define CRCR_CS (1 << 1)</span><br><span> #define CRCR_CA (1 << 2)</span><br><span> #define CRCR_CRR (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">- u8 res2[0x2f-0x20+1];</span><br><span style="color: hsl(0, 100%, 40%);">- u32 dcbaap_lo;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 dcbaap_hi;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 res2[0x2f-0x20+1]; /* 0x20 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dcbaap_lo; /* 0x30 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dcbaap_hi; /* 0x34 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 config; /* 0x38 */</span><br><span> #define CONFIG_LP_MASK_MaxSlotsEn 0xff</span><br><span style="color: hsl(0, 100%, 40%);">- u8 res3[0x3ff-0x3c+1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 res3[0x3ff-0x3c+1]; /* 0x3C */</span><br><span> struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 portsc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 portsc; /* 0x400 + 4 * port */</span><br><span> #define PORTSC_CCS (1 << 0)</span><br><span> #define PORTSC_PED (1 << 1)</span><br><span> // BIT 2 rsvdZ</span><br><span>@@ -443,9 +443,9 @@</span><br><span> #define PORTSC_DR (1 << 30)</span><br><span> #define PORTSC_WPR (1 << 31)</span><br><span> #define PORTSC_RW_MASK (PORTSC_PR | PORTSC_PLS_MASK | PORTSC_PP | PORTSC_PIC_MASK | PORTSC_LWS | PORTSC_WCE | PORTSC_WDE | PORTSC_WOE)</span><br><span style="color: hsl(0, 100%, 40%);">- u32 portpmsc;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 portli;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 res;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 portpmsc; /* 0x404 + 4 * port */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 portli; /* 0x408 + 4 * port */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 res; /* 0x40C + 4 * port */</span><br><span> } __packed prs[];</span><br><span> } __packed *opreg;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27474">change 27474</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6 </div>
<div style="display:none"> Gerrit-Change-Number: 27474 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Raul Rangel <rrangel@chromium.org> </div>