[coreboot-gerrit] Change in coreboot[master]: Kconfig: Make the EM100 config option common

[Simon Glass (Code Review)]

Simon Glass has uploaded this change for review. ( https://review.coreboot.org/27467


Change subject: Kconfig: Make the EM100 config option common
......................................................................

Kconfig: Make the EM100 config option common

This applied to AMD devices as well as Intel, although the mechanism is
different. Move the option to a common place.

BUG=b:111363976
TEST=USE=em100-mode emerge-reef coreboot
See that a message appears:
 * Enabling em100 mode (slow SPI flash)

Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd
Signed-off-by: Simon Glass <sjg at chromium.org>
---
M src/Kconfig
M src/southbridge/intel/common/firmware/Kconfig
2 files changed, 14 insertions(+), 6 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/27467/1

diff --git a/src/Kconfig b/src/Kconfig
index 24b2106..c8ce14f 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1024,6 +1024,20 @@
 	  Add the compiler switch `-gnata` to compile code guarded by
 	  `pragma Debug`.
 
+config EM100
+	bool "Configure image for EM100 usage"
+	depends on (HAVE_INTEL_FIRMWARE && HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD) || \
+		SOC_AMD_COMMON
+	help
+	  The Dediprog EM100 SPI emulator allows fast loading of new SPI images
+	  over USB. However it only supports a maximum SPI clock of 20MHz and
+	  single data output. Enable this option to use a 20MHz SPI clock and
+	  disable "Dual Output Fast Read" Support.
+
+	  On AMD platforms this changes the SPI speed at run-time if the
+	  mainboard code supports this. On supported Intel platforms this works
+	  by changing the settings in the descriptor.bin file.
+
 endmenu
 
 
diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig
index 30c9aaf..b65e7af 100644
--- a/src/southbridge/intel/common/firmware/Kconfig
+++ b/src/southbridge/intel/common/firmware/Kconfig
@@ -34,12 +34,6 @@
 	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
 	depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD
 
-config EM100
-	bool "Configure IFD for EM100 usage"
-	depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD
-	help
-	  Set SPI frequency to 20MHz and disable Dual Output Fast Read Support
-
 config HAVE_ME_BIN
 	bool "Add Intel ME/TXE firmware"
 	depends on HAVE_IFD_BIN

-- 
To view, visit https://review.coreboot.org/27467
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd
Gerrit-Change-Number: 27467
Gerrit-PatchSet: 1
Gerrit-Owner: Simon Glass <sjg at chromium.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180712/45daa33d/attachment.html>