[coreboot-gerrit] Change in coreboot[master]: stoneyridge: Add support for Dediprog em100

[Simon Glass (Code Review)]

Simon Glass has uploaded this change for review. ( https://review.coreboot.org/27466


Change subject: stoneyridge: Add support for Dediprog em100
......................................................................

stoneyridge: Add support for Dediprog em100

This device claims to run at 75MHz with dual read, but it is not always
reliable. Add an option to change the SPI flash speed to 16MHz, to avoid
any problems.

BUG=b:111363976
TEST=manually try to get my em100 running (it doesn't yet)

Change-Id: I78d3d32c467aac82c72d31c773bfb0f69808aed4
Signed-off-by: Simon Glass <sjg at chromium.org>
---
M src/mainboard/google/kahlee/bootblock/bootblock.c
M src/soc/amd/stoneyridge/Kconfig
2 files changed, 37 insertions(+), 12 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/27466/1

diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index 7e6524d..9d767d0 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -34,19 +34,36 @@
 
 void bootblock_mainboard_init(void)
 {
-	/*
-	 * W25Q128FW Setup
-	 * Normal Read 40MHz
-	 * Fast Read 104MHz
-	 * Dual Read IO (1-2-2)
-	 */
-	sb_read_mode(SPI_READ_MODE_DUAL122);
+	if (IS_ENABLED(CONFIG_EM100)) {
+		/*
+		 * We should be able to rely on defaults, but it seems safer
+		 * to explicitly set up these registers.
+		 *
+		 * Usage:
+		 * sudo emerge em100
+		 * sudo em100 -s -c W25Q128FW  -d \
+		 *	/build/grunt/firmware/image-grunt.serial.bin -r
+		 */
+		sb_read_mode(SPI_READ_MODE_NOM);
+		sb_set_spi100(SPI_SPEED_16M,		/* Normal */
+				SPI_SPEED_16M,		/* Fast   */
+				SPI_SPEED_16M,		/* AltIO  */
+				SPI_SPEED_66M);		/* TPM    */
+	} else {
+		/*
+		* W25Q128FW Setup
+		* Normal Read 40MHz
+		* Fast Read 104MHz
+		* Dual Read IO (1-2-2)
+		*/
+		sb_read_mode(SPI_READ_MODE_DUAL122);
 
-	/* Set SPI speeds before verstage. Needed for TPM */
-	sb_set_spi100(SPI_SPEED_33M,		/* Normal */
-			SPI_SPEED_66M,		/* Fast   */
-			SPI_SPEED_66M,		/* AltIO  */
-			SPI_SPEED_66M);		/* TPM    */
+		/* Set SPI speeds before verstage. Needed for TPM */
+		sb_set_spi100(SPI_SPEED_33M,		/* Normal */
+				SPI_SPEED_66M,		/* Fast   */
+				SPI_SPEED_66M,		/* AltIO  */
+				SPI_SPEED_66M);		/* TPM    */
+	}
 
 	/* Setup TPM decode before verstage */
 	sb_tpm_decode_spi();
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 05c3043..08e51cd 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -394,4 +394,12 @@
 	  vendorcode/amd/pi/00670F00/ will be compiled or only
 	  selected procedures of source files (minimum required).
 
+config EM100
+	bool "Configure image for EM100 usage"
+	help
+	  The Dediprog EM100 SPI emulator allows fast loading of new SPI images
+	  over USB. However it only supports a maximum SPI clock of 20MHz and
+	  single data output. Enable this option to use a 20MHz SPI clock and
+	  disable "Dual Output Fast Read" Support
+
 endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I78d3d32c467aac82c72d31c773bfb0f69808aed4
Gerrit-Change-Number: 27466
Gerrit-PatchSet: 1
Gerrit-Owner: Simon Glass <sjg at chromium.org>
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