[coreboot-gerrit] Change in coreboot[master]: riscv: add support for modifying compiler options

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27442


Change subject: riscv: add support for modifying compiler options
......................................................................

riscv: add support for modifying compiler options

Each HART of a SoC like fu540 supports a different ISA.
In order for the coreboot's code can run on each core, need to modify the
compile options. So add this code.

Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/Kconfig
M src/arch/riscv/Makefile.inc
M src/soc/sifive/fu540/Kconfig
M src/soc/ucb/riscv/Kconfig
4 files changed, 34 insertions(+), 14 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27442/1

diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index 2513c50..b060ba34 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -2,12 +2,14 @@
 	bool
 	default n
 
-config ARCH_RISCV_COMPRESSED
-	bool
-	default n
-	help
-	  Enable this option if your RISC-V processor supports compressed
-	  instructions (RVC). Currently, this enables RVC for all stages.
+config RISCV_ARCH
+	string
+
+config RISCV_ABI
+	string
+
+config RISCV_CMODEL
+	string
 
 config ARCH_BOOTBLOCK_RISCV
 	bool
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 4b2ff03..e6e0d42 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -23,15 +23,9 @@
 check-ramstage-overlap-regions += stack
 endif
 
-riscv_arch = rv64imafd
+riscv_flags = -I$(src)/arch/riscv/ -mcmodel=$(CONFIG_RISCV_CMODEL) -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
 
-ifeq ($(CONFIG_ARCH_RISCV_COMPRESSED),y)
-	riscv_arch := $(riscv_arch)c
-endif
-
-riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=$(riscv_arch)
-
-riscv_asm_flags = -march=$(riscv_arch)
+riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
 
 ################################################################################
 ## bootblock
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig
index d247c28..b589fab 100644
--- a/src/soc/sifive/fu540/Kconfig
+++ b/src/soc/sifive/fu540/Kconfig
@@ -23,4 +23,16 @@
 
 if SOC_SIFIVE_FU540
 
+config RISCV_ARCH
+	string
+	default "rv64imac"
+
+config RISCV_ABI
+	string
+	default "lp64"
+
+config RISCV_CMODEL
+	string
+	default "medany"
+
 endif
diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig
index ff50f6f..4b0cdb7 100644
--- a/src/soc/ucb/riscv/Kconfig
+++ b/src/soc/ucb/riscv/Kconfig
@@ -10,4 +10,16 @@
 
 if SOC_UCB_RISCV
 
+config RISCV_ARCH
+	string
+	default "rv64imafd"
+
+config RISCV_ABI
+	string
+	default "lp64"
+
+config RISCV_CMODEL
+	string
+	default "medany"
+
 endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b
Gerrit-Change-Number: 27442
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
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