[coreboot-gerrit] Change in coreboot[master]: riscv: exception handle support SMP

[Xiang Wang (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/27441

to look at the new patch set (#2).

Change subject: riscv: exception handle support SMP
......................................................................

riscv: exception handle support SMP

fix exception handle not support SMP for RISC-V.

Change-Id: I053138c6d778413d125e91689da330b1ac857027
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/trap_util.S
1 file changed, 97 insertions(+), 108 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/27441/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I053138c6d778413d125e91689da330b1ac857027
Gerrit-Change-Number: 27441
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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