<p>Xiang Wang <strong>uploaded patch set #2</strong> to this change.</p><p><a href="https://review.coreboot.org/27441">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">riscv: exception handle support SMP<br><br>fix exception handle not support SMP for RISC-V.<br><br>Change-Id: I053138c6d778413d125e91689da330b1ac857027<br>Signed-off-by: Xiang Wang <wxjstz@126.com><br>---<br>M src/arch/riscv/trap_util.S<br>1 file changed, 97 insertions(+), 108 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/27441/2</pre><p>To view, visit <a href="https://review.coreboot.org/27441">change 27441</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27441"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newpatchset </div>
<div style="display:none"> Gerrit-Change-Id: I053138c6d778413d125e91689da330b1ac857027 </div>
<div style="display:none"> Gerrit-Change-Number: 27441 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Xiang Wang <wxjstz@126.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>