<p>Xiang Wang has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27442">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">riscv: add support for modifying compiler options<br><br>Each HART of a SoC like fu540 supports a different ISA.<br>In order for the coreboot's code can run on each core, need to modify the<br>compile options. So add this code.<br><br>Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b<br>Signed-off-by: Xiang Wang <wxjstz@126.com><br>---<br>M src/arch/riscv/Kconfig<br>M src/arch/riscv/Makefile.inc<br>M src/soc/sifive/fu540/Kconfig<br>M src/soc/ucb/riscv/Kconfig<br>4 files changed, 34 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27442/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig</span><br><span>index 2513c50..b060ba34 100644</span><br><span>--- a/src/arch/riscv/Kconfig</span><br><span>+++ b/src/arch/riscv/Kconfig</span><br><span>@@ -2,12 +2,14 @@</span><br><span> bool</span><br><span> default n</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config ARCH_RISCV_COMPRESSED</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- default n</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- Enable this option if your RISC-V processor supports compressed</span><br><span style="color: hsl(0, 100%, 40%);">- instructions (RVC). Currently, this enables RVC for all stages.</span><br><span style="color: hsl(120, 100%, 40%);">+config RISCV_ARCH</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config RISCV_ABI</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config RISCV_CMODEL</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span> </span><br><span> config ARCH_BOOTBLOCK_RISCV</span><br><span> bool</span><br><span>diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc</span><br><span>index 4b2ff03..e6e0d42 100644</span><br><span>--- a/src/arch/riscv/Makefile.inc</span><br><span>+++ b/src/arch/riscv/Makefile.inc</span><br><span>@@ -23,15 +23,9 @@</span><br><span> check-ramstage-overlap-regions += stack</span><br><span> endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-riscv_arch = rv64imafd</span><br><span style="color: hsl(120, 100%, 40%);">+riscv_flags = -I$(src)/arch/riscv/ -mcmodel=$(CONFIG_RISCV_CMODEL) -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ifeq ($(CONFIG_ARCH_RISCV_COMPRESSED),y)</span><br><span style="color: hsl(0, 100%, 40%);">- riscv_arch := $(riscv_arch)c</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=$(riscv_arch)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-riscv_asm_flags = -march=$(riscv_arch)</span><br><span style="color: hsl(120, 100%, 40%);">+riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)</span><br><span> </span><br><span> ################################################################################</span><br><span> ## bootblock</span><br><span>diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig</span><br><span>index d247c28..b589fab 100644</span><br><span>--- a/src/soc/sifive/fu540/Kconfig</span><br><span>+++ b/src/soc/sifive/fu540/Kconfig</span><br><span>@@ -23,4 +23,16 @@</span><br><span> </span><br><span> if SOC_SIFIVE_FU540</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config RISCV_ARCH</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "rv64imac"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config RISCV_ABI</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "lp64"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config RISCV_CMODEL</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "medany"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig</span><br><span>index ff50f6f..4b0cdb7 100644</span><br><span>--- a/src/soc/ucb/riscv/Kconfig</span><br><span>+++ b/src/soc/ucb/riscv/Kconfig</span><br><span>@@ -10,4 +10,16 @@</span><br><span> </span><br><span> if SOC_UCB_RISCV</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config RISCV_ARCH</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "rv64imafd"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config RISCV_ABI</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "lp64"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config RISCV_CMODEL</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "medany"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27442">change 27442</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b </div>
<div style="display:none"> Gerrit-Change-Number: 27442 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Xiang Wang <wxjstz@126.com> </div>