[coreboot-gerrit] Change in coreboot[master]: mediatek: Share GPIO code among similar SOCs
Tristan Hsieh (Code Review)
gerrit at coreboot.org
Mon Jul 9 13:25:08 CEST 2018
Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27416
Change subject: mediatek: Share GPIO code among similar SOCs
......................................................................
mediatek: Share GPIO code among similar SOCs
Refactor GPIO code which will be reused among similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0
Signed-off-by: Tristan Shieh <tristan.shieh at mediatek.com>
---
M src/mainboard/google/oak/bootblock.c
A src/soc/mediatek/common/gpio.c
M src/soc/mediatek/mt8173/Makefile.inc
M src/soc/mediatek/mt8173/gpio.c
M src/soc/mediatek/mt8173/gpio_init.c
M src/soc/mediatek/mt8173/include/soc/gpio.h
M src/soc/mediatek/mt8173/include/soc/pinmux.h
7 files changed, 440 insertions(+), 293 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/27416/1
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index fe9c9ba..8034526 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -44,9 +44,9 @@
* 3: 16mA
*/
/* EINT4: 0x10005B20[14:13] */
- clrsetbits_le16(&mt8173_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
+ clrsetbits_le16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
/* EINT5~EINT9: 0x10005B30[2:1] */
- clrsetbits_le16(&mt8173_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
+ clrsetbits_le16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
gpio_set_pull(PAD_EINT4, GPIO_PULL_ENABLE, GPIO_PULL_UP);
gpio_set_pull(PAD_EINT5, GPIO_PULL_ENABLE, GPIO_PULL_UP);
diff --git a/src/soc/mediatek/common/gpio.c b/src/soc/mediatek/common/gpio.c
new file mode 100644
index 0000000..e6f99cb
--- /dev/null
+++ b/src/soc/mediatek/common/gpio.c
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <gpio.h>
+
+enum {
+ GPIO_DIRECTION_IN = 0,
+ GPIO_DIRECTION_OUT = 1,
+};
+
+enum {
+ GPIO_MODE = 0,
+};
+
+static void pos_bit_calc(gpio_t gpio, u32 *pos, u32 *bit)
+{
+ *pos = GPIO_GET_ID(gpio) / MAX_GPIO_REG_BITS;
+ *bit = GPIO_GET_ID(gpio) % MAX_GPIO_REG_BITS;
+}
+
+static void pos_bit_calc_for_mode(gpio_t gpio, u32 *pos, u32 *bit)
+{
+ *pos = GPIO_GET_ID(gpio) / MAX_GPIO_MODE_PER_REG;
+ *bit = (GPIO_GET_ID(gpio) % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS;
+}
+
+static s32 gpio_set_dir(gpio_t gpio, u32 dir)
+{
+ u32 pos;
+ u32 bit;
+ u32 *reg;
+
+ pos_bit_calc(gpio, &pos, &bit);
+
+ if (dir == GPIO_DIRECTION_IN)
+ reg = &mtk_gpio->dir[pos].rst;
+ else
+ reg = &mtk_gpio->dir[pos].set;
+
+ write32(reg, 1L << bit);
+
+ return 0;
+}
+
+void gpio_set_mode(gpio_t gpio, int mode)
+{
+ u32 pos;
+ u32 bit;
+ u32 mask = (1L << GPIO_MODE_BITS) - 1;
+
+ pos_bit_calc_for_mode(gpio, &pos, &bit);
+
+ clrsetbits_le32(&mtk_gpio->mode[pos].val,
+ mask << bit, mode << bit);
+}
+
+int gpio_get(gpio_t gpio)
+{
+ u32 pos;
+ u32 bit;
+ u32 *reg;
+ u32 data;
+
+ pos_bit_calc(gpio, &pos, &bit);
+
+ reg = &mtk_gpio->din[pos].val;
+ data = read32(reg);
+
+ return (data & (1L << bit)) ? 1 : 0;
+}
+
+void gpio_set(gpio_t gpio, int output)
+{
+ u32 pos;
+ u32 bit;
+ u32 *reg;
+
+ pos_bit_calc(gpio, &pos, &bit);
+
+ if (output == 0)
+ reg = &mtk_gpio->dout[pos].rst;
+ else
+ reg = &mtk_gpio->dout[pos].set;
+
+ write32(reg, 1L << bit);
+}
+
+void gpio_input_pulldown(gpio_t gpio)
+{
+ gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
+ gpio_set_dir(gpio, GPIO_DIRECTION_IN);
+ gpio_set_mode(gpio, GPIO_MODE);
+}
+
+void gpio_input_pullup(gpio_t gpio)
+{
+ gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+ gpio_set_dir(gpio, GPIO_DIRECTION_IN);
+ gpio_set_mode(gpio, GPIO_MODE);
+}
+
+void gpio_input(gpio_t gpio)
+{
+ gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN);
+ gpio_set_dir(gpio, GPIO_DIRECTION_IN);
+ gpio_set_mode(gpio, GPIO_MODE);
+}
+
+void gpio_output(gpio_t gpio, int value)
+{
+ gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN);
+ gpio_set(gpio, value);
+ gpio_set_dir(gpio, GPIO_DIRECTION_OUT);
+ gpio_set_mode(gpio, GPIO_MODE);
+}
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index 56c966a..ae7fd5b 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -27,7 +27,7 @@
bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c
endif
-bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c
+bootblock-y += ../common/gpio.c gpio.c gpio_init.c pmic_wrap.c mt6391.c
bootblock-y += ../common/wdt.c
bootblock-y += mmu_operations.c
@@ -42,7 +42,7 @@
verstage-y += timer.c
verstage-y += ../common/wdt.c
verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
-verstage-y += gpio.c
+verstage-y += ../common/gpio.c gpio.c
################################################################################
@@ -54,7 +54,7 @@
romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
romstage-y += ../common/cbmem.c
romstage-y += spi.c
-romstage-y += gpio.c
+romstage-y += ../common/gpio.c gpio.c
romstage-y += pmic_wrap.c mt6391.c
romstage-y += memory.c
romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c
@@ -73,7 +73,7 @@
ramstage-y += pmic_wrap.c mt6391.c i2c.c
ramstage-y += mt6311.c
ramstage-y += da9212.c
-ramstage-y += gpio.c
+ramstage-y += ../common/gpio.c gpio.c
ramstage-y += ../common/wdt.c
ramstage-y += pll.c
ramstage-y += rtc.c
diff --git a/src/soc/mediatek/mt8173/gpio.c b/src/soc/mediatek/mt8173/gpio.c
index c5ca08b..f3bbeb2 100644
--- a/src/soc/mediatek/mt8173/gpio.c
+++ b/src/soc/mediatek/mt8173/gpio.c
@@ -14,80 +14,38 @@
*/
#include <arch/io.h>
#include <assert.h>
-#include <console/console.h>
#include <gpio.h>
#include <types.h>
-#include <soc/addressmap.h>
-#include <soc/gpio.h>
enum {
- MAX_8173_GPIO = 134,
- MAX_GPIO_REG_BITS = 16,
- MAX_GPIO_MODE_PER_REG = 5,
- GPIO_MODE_BITS = 3,
+ MAX_GPIO_NUMBER = 134,
MAX_EINT_REG_BITS = 32,
};
-enum {
- GPIO_DIRECTION_IN = 0,
- GPIO_DIRECTION_OUT = 1,
-};
-
-enum {
- GPIO_MODE = 0,
-};
-
-static void pos_bit_calc(u32 pin, u32 *pos, u32 *bit)
+static void pos_bit_calc(gpio_t gpio, u32 *pos, u32 *bit)
{
- *pos = pin / MAX_GPIO_REG_BITS;
- *bit = pin % MAX_GPIO_REG_BITS;
+ *pos = GPIO_GET_ID(gpio) / MAX_GPIO_REG_BITS;
+ *bit = GPIO_GET_ID(gpio) % MAX_GPIO_REG_BITS;
}
-static void pos_bit_calc_for_mode(u32 pin, u32 *pos, u32 *bit)
+static void pos_bit_calc_for_eint(gpio_t gpio, u32 *pos, u32 *bit)
{
- *pos = pin / MAX_GPIO_MODE_PER_REG;
- *bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS;
+ *pos = GPIO_GET_ID(gpio) / MAX_EINT_REG_BITS;
+ *bit = GPIO_GET_ID(gpio) % MAX_EINT_REG_BITS;
}
-static void pos_bit_calc_for_eint(u32 pin, u32 *pos, u32 *bit)
-{
- *pos = pin / MAX_EINT_REG_BITS;
- *bit = pin % MAX_EINT_REG_BITS;
-}
-
-static s32 gpio_set_dir(u32 pin, u32 dir)
-{
- u32 pos;
- u32 bit;
- u16 *reg;
-
- assert(pin <= MAX_8173_GPIO);
-
- pos_bit_calc(pin, &pos, &bit);
-
- if (dir == GPIO_DIRECTION_IN)
- reg = &mt8173_gpio->dir[pos].rst;
- else
- reg = &mt8173_gpio->dir[pos].set;
-
- write16(reg, 1L << bit);
-
- return 0;
-}
-
-void gpio_set_pull(gpio_t pin, enum pull_enable enable,
+void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
enum pull_select select)
{
u32 pos;
u32 bit;
- u16 *en_reg, *sel_reg;
+ u32 *en_reg, *sel_reg;
+ u32 pin = GPIO_GET_ID(gpio);
- assert(pin <= MAX_8173_GPIO);
-
- pos_bit_calc(pin, &pos, &bit);
+ pos_bit_calc(gpio, &pos, &bit);
if (enable == GPIO_PULL_DISABLE) {
- en_reg = &mt8173_gpio->pullen[pos].rst;
+ en_reg = &mtk_gpio->pullen[pos].rst;
} else {
/* These pins' pulls can't be set through GPIO controller. */
assert(pin < 22 || pin > 27);
@@ -97,100 +55,21 @@
assert(pin < 100 || pin > 105);
assert(pin < 119 || pin > 124);
- en_reg = &mt8173_gpio->pullen[pos].set;
+ en_reg = &mtk_gpio->pullen[pos].set;
sel_reg = (select == GPIO_PULL_DOWN) ?
- (&mt8173_gpio->pullsel[pos].rst) :
- (&mt8173_gpio->pullsel[pos].set);
+ (&mtk_gpio->pullsel[pos].rst) :
+ (&mtk_gpio->pullsel[pos].set);
write16(sel_reg, 1L << bit);
}
write16(en_reg, 1L << bit);
}
-int gpio_get(gpio_t pin)
-{
- u32 pos;
- u32 bit;
- u16 *reg;
- s32 data;
-
- assert(pin <= MAX_8173_GPIO);
-
- pos_bit_calc(pin, &pos, &bit);
-
- reg = &mt8173_gpio->din[pos].val;
- data = read32(reg);
-
- return (data & (1L << bit)) ? 1 : 0;
-}
-
-void gpio_set(gpio_t pin, int output)
-{
- u32 pos;
- u32 bit;
- u16 *reg;
-
- assert(pin <= MAX_8173_GPIO);
-
- pos_bit_calc(pin, &pos, &bit);
-
- if (output == 0)
- reg = &mt8173_gpio->dout[pos].rst;
- else
- reg = &mt8173_gpio->dout[pos].set;
- write16(reg, 1L << bit);
-}
-
-void gpio_set_mode(gpio_t pin, int mode)
-{
- u32 pos;
- u32 bit;
- u32 mask = (1L << GPIO_MODE_BITS) - 1;
-
- assert(pin <= MAX_8173_GPIO);
-
- pos_bit_calc_for_mode(pin, &pos, &bit);
-
- clrsetbits_le32(&mt8173_gpio->mode[pos].val,
- mask << bit, mode << bit);
-}
-
-void gpio_input_pulldown(gpio_t gpio)
-{
- gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
- gpio_set_dir(gpio, GPIO_DIRECTION_IN);
- gpio_set_mode(gpio, GPIO_MODE);
-}
-
-void gpio_input_pullup(gpio_t gpio)
-{
- gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP);
- gpio_set_dir(gpio, GPIO_DIRECTION_IN);
- gpio_set_mode(gpio, GPIO_MODE);
-}
-
-void gpio_input(gpio_t gpio)
-{
- gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN);
- gpio_set_dir(gpio, GPIO_DIRECTION_IN);
- gpio_set_mode(gpio, GPIO_MODE);
-}
-
-void gpio_output(gpio_t gpio, int value)
-{
- gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN);
- gpio_set(gpio, value);
- gpio_set_dir(gpio, GPIO_DIRECTION_OUT);
- gpio_set_mode(gpio, GPIO_MODE);
-}
-
int gpio_eint_poll(gpio_t gpio)
{
u32 pos;
u32 bit;
u32 status;
- assert(gpio <= MAX_8173_GPIO);
-
pos_bit_calc_for_eint(gpio, &pos, &bit);
status = (read32(&mt8173_eint->sta.regs[pos]) >> bit) & 0x1;
@@ -206,8 +85,6 @@
u32 pos;
u32 bit, mask;
- assert(gpio <= MAX_8173_GPIO);
-
pos_bit_calc_for_eint(gpio, &pos, &bit);
mask = 1 << bit;
diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c
index 7f8313a..79ed316 100644
--- a/src/soc/mediatek/mt8173/gpio_init.c
+++ b/src/soc/mediatek/mt8173/gpio_init.c
@@ -49,18 +49,18 @@
/* EXMD control reg */
if (ext_power == GPIO_EINT_1P8V) {
/* exmd_ctrl[9:4] = b`000000, [3:0] = b`1010 */
- write16(&mt8173_gpio->exmd_ctrl[0].rst, 0x3F5);
- write16(&mt8173_gpio->exmd_ctrl[0].set, 0xA);
+ write16(&mtk_gpio->exmd_ctrl[0].rst, 0x3F5);
+ write16(&mtk_gpio->exmd_ctrl[0].set, 0xA);
} else if (ext_power == GPIO_EINT_3P3V) {
/* exmd_ctrl[9:4] = b`001100, [3:0] = b`1010 */
- write16(&mt8173_gpio->exmd_ctrl[0].rst, 0x335);
- write16(&mt8173_gpio->exmd_ctrl[0].set, 0xCA);
+ write16(&mtk_gpio->exmd_ctrl[0].rst, 0x335);
+ write16(&mtk_gpio->exmd_ctrl[0].set, 0xCA);
}
/* other R/TDSEL */
/* msdc2_ctrl5 , bit[3:0] = b`1010 */
- write16(&mt8173_gpio->msdc2_ctrl5.set, 0xA);
- write16(&mt8173_gpio->msdc2_ctrl5.rst, 0x5);
+ write16(&mtk_gpio->msdc2_ctrl5.set, 0xA);
+ write16(&mtk_gpio->msdc2_ctrl5.rst, 0x5);
}
void gpio_init(enum external_power ext_power)
diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h
index 1c05e48..46361ce 100644
--- a/src/soc/mediatek/mt8173/include/soc/gpio.h
+++ b/src/soc/mediatek/mt8173/include/soc/gpio.h
@@ -19,6 +19,12 @@
#include <stdlib.h>
#include <soc/addressmap.h>
+enum {
+ MAX_GPIO_REG_BITS = 16,
+ MAX_GPIO_MODE_PER_REG = 5,
+ GPIO_MODE_BITS = 3,
+};
+
enum pull_enable {
GPIO_PULL_DISABLE = 0,
GPIO_PULL_ENABLE = 1,
@@ -34,15 +40,151 @@
GPIO_EINT_1P8V = 1,
};
-typedef u32 gpio_t;
+#define GPIO_GET_ID(x) (x)
+
+typedef enum {
+ GPIO_PAD_0 = 0,
+ GPIO_PAD_1 = 1,
+ GPIO_PAD_2 = 2,
+ GPIO_PAD_3 = 3,
+ GPIO_PAD_4 = 4,
+ GPIO_PAD_5 = 5,
+ GPIO_PAD_6 = 6,
+ GPIO_PAD_7 = 7,
+ GPIO_PAD_8 = 8,
+ GPIO_PAD_9 = 9,
+ GPIO_PAD_10 = 10,
+ GPIO_PAD_11 = 11,
+ GPIO_PAD_12 = 12,
+ GPIO_PAD_13 = 13,
+ GPIO_PAD_14 = 14,
+ GPIO_PAD_15 = 15,
+ GPIO_PAD_16 = 16,
+ GPIO_PAD_17 = 17,
+ GPIO_PAD_18 = 18,
+ GPIO_PAD_19 = 19,
+ GPIO_PAD_20 = 20,
+ GPIO_PAD_21 = 21,
+ GPIO_PAD_22 = 22,
+ GPIO_PAD_23 = 23,
+ GPIO_PAD_24 = 24,
+ GPIO_PAD_25 = 25,
+ GPIO_PAD_26 = 26,
+ GPIO_PAD_27 = 27,
+ GPIO_PAD_28 = 28,
+ GPIO_PAD_29 = 29,
+ GPIO_PAD_30 = 30,
+ GPIO_PAD_31 = 31,
+ GPIO_PAD_32 = 32,
+ GPIO_PAD_33 = 33,
+ GPIO_PAD_34 = 34,
+ GPIO_PAD_35 = 35,
+ GPIO_PAD_36 = 36,
+ GPIO_PAD_37 = 37,
+ GPIO_PAD_38 = 38,
+ GPIO_PAD_39 = 39,
+ GPIO_PAD_40 = 40,
+ GPIO_PAD_41 = 41,
+ GPIO_PAD_42 = 42,
+ GPIO_PAD_43 = 43,
+ GPIO_PAD_44 = 44,
+ GPIO_PAD_45 = 45,
+ GPIO_PAD_46 = 46,
+ GPIO_PAD_47 = 47,
+ GPIO_PAD_48 = 48,
+ GPIO_PAD_49 = 49,
+ GPIO_PAD_50 = 50,
+ GPIO_PAD_51 = 51,
+ GPIO_PAD_52 = 52,
+ GPIO_PAD_53 = 53,
+ GPIO_PAD_54 = 54,
+ GPIO_PAD_55 = 55,
+ GPIO_PAD_56 = 56,
+ GPIO_PAD_57 = 57,
+ GPIO_PAD_58 = 58,
+ GPIO_PAD_59 = 59,
+ GPIO_PAD_60 = 60,
+ GPIO_PAD_61 = 61,
+ GPIO_PAD_62 = 62,
+ GPIO_PAD_63 = 63,
+ GPIO_PAD_64 = 64,
+ GPIO_PAD_65 = 65,
+ GPIO_PAD_66 = 66,
+ GPIO_PAD_67 = 67,
+ GPIO_PAD_68 = 68,
+ GPIO_PAD_69 = 69,
+ GPIO_PAD_70 = 70,
+ GPIO_PAD_71 = 71,
+ GPIO_PAD_72 = 72,
+ GPIO_PAD_73 = 73,
+ GPIO_PAD_74 = 74,
+ GPIO_PAD_75 = 75,
+ GPIO_PAD_76 = 76,
+ GPIO_PAD_77 = 77,
+ GPIO_PAD_78 = 78,
+ GPIO_PAD_79 = 79,
+ GPIO_PAD_80 = 80,
+ GPIO_PAD_81 = 81,
+ GPIO_PAD_82 = 82,
+ GPIO_PAD_83 = 83,
+ GPIO_PAD_84 = 84,
+ GPIO_PAD_85 = 85,
+ GPIO_PAD_86 = 86,
+ GPIO_PAD_87 = 87,
+ GPIO_PAD_88 = 88,
+ GPIO_PAD_89 = 89,
+ GPIO_PAD_90 = 90,
+ GPIO_PAD_91 = 91,
+ GPIO_PAD_92 = 92,
+ GPIO_PAD_93 = 93,
+ GPIO_PAD_94 = 94,
+ GPIO_PAD_95 = 95,
+ GPIO_PAD_96 = 96,
+ GPIO_PAD_97 = 97,
+ GPIO_PAD_98 = 98,
+ GPIO_PAD_99 = 99,
+ GPIO_PAD_100 = 100,
+ GPIO_PAD_101 = 101,
+ GPIO_PAD_102 = 102,
+ GPIO_PAD_103 = 103,
+ GPIO_PAD_104 = 104,
+ GPIO_PAD_105 = 105,
+ GPIO_PAD_106 = 106,
+ GPIO_PAD_107 = 107,
+ GPIO_PAD_108 = 108,
+ GPIO_PAD_109 = 109,
+ GPIO_PAD_110 = 110,
+ GPIO_PAD_111 = 111,
+ GPIO_PAD_112 = 112,
+ GPIO_PAD_113 = 113,
+ GPIO_PAD_114 = 114,
+ GPIO_PAD_115 = 115,
+ GPIO_PAD_116 = 116,
+ GPIO_PAD_117 = 117,
+ GPIO_PAD_118 = 118,
+ GPIO_PAD_119 = 119,
+ GPIO_PAD_120 = 120,
+ GPIO_PAD_121 = 121,
+ GPIO_PAD_122 = 122,
+ GPIO_PAD_123 = 123,
+ GPIO_PAD_124 = 124,
+ GPIO_PAD_125 = 125,
+ GPIO_PAD_126 = 126,
+ GPIO_PAD_127 = 127,
+ GPIO_PAD_128 = 128,
+ GPIO_PAD_129 = 129,
+ GPIO_PAD_130 = 130,
+ GPIO_PAD_131 = 131,
+ GPIO_PAD_132 = 132,
+ GPIO_PAD_133 = 133,
+ GPIO_PAD_134 = 134,
+} gpio_t;
struct val_regs {
- uint16_t val;
- uint16_t align1;
- uint16_t set;
- uint16_t align2;
- uint16_t rst;
- uint16_t align3[3];
+ uint32_t val;
+ uint32_t set;
+ uint32_t rst;
+ uint32_t align;
};
struct gpio_regs {
@@ -80,7 +222,7 @@
check_member(gpio_regs, msdc2_ctrl5, 0xcb0);
check_member(gpio_regs, hsic_ctrl[3], 0xe50);
-static struct gpio_regs *const mt8173_gpio = (void *)(GPIO_BASE);
+static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE);
void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
enum pull_select select);
diff --git a/src/soc/mediatek/mt8173/include/soc/pinmux.h b/src/soc/mediatek/mt8173/include/soc/pinmux.h
index 07c53a8..21f6ce8 100644
--- a/src/soc/mediatek/mt8173/include/soc/pinmux.h
+++ b/src/soc/mediatek/mt8173/include/soc/pinmux.h
@@ -26,141 +26,141 @@
PAD_##name##_FUNC_##func7 = 7
enum {
- PINMUX_CONSTANTS(0, EINT0, IRDA_PDN, I2S1_WS, AUD_SPDIF, UTXD0, RES5, RES6, DBG_MON_A_20),
- PINMUX_CONSTANTS(1, EINT1, IRDA_RXD, I2S1_BCK, SDA5, URXD0, RES5, RES6, DBG_MON_A_21),
- PINMUX_CONSTANTS(2, EINT2, IRDA_TXD, I2S1_MCK, SCL5, UTXD3, RES5, RES6, DBG_MON_A_22),
- PINMUX_CONSTANTS(3, EINT3, DSI1_TE, I2S1_DO_1, SDA3, URXD3, RES5, RES6, DBG_MON_A_23),
- PINMUX_CONSTANTS(4, EINT4, DISP_PWM1, I2S1_DO_2, SCL3, UCTS3, RES5, SFWP_B, RES7),
- PINMUX_CONSTANTS(5, EINT5, PCM1_CLK, I2S2_WS, SPI_CK_3, URTS3, AP_MD32_JTAG_TMS, SFOUT, RES7),
- PINMUX_CONSTANTS(6, EINT6, PCM1_SYNC, I2S2_BCK, SPI_MI_3, RES4, AP_MD32_JTAG_TCK, SFCS0, RES7),
- PINMUX_CONSTANTS(7, EINT7, PCM1_DI, I2S2_DI_1, SPI_MO_3, RES4, AP_MD32_JTAG_TDI, SFHOLD, RES7),
- PINMUX_CONSTANTS(8, EINT8, PCM1_DO, I2S2_DI_2, SPI_CS_3, AUD_SPDIF, AP_MD32_JTAG_TDO, SFIN, RES7),
- PINMUX_CONSTANTS(9, EINT9, USB_DRVVBUS_P0, I2S2_MCK, RES3, USB_DRVVBUS_P1, AP_MD32_JTAG_TRST, SFCK, RES7),
- PINMUX_CONSTANTS(10, EINT10, CLKM0, DSI1_TE, DISP_PWM1, PWM4, IRDA_RXD, RES6, RES7),
- PINMUX_CONSTANTS(11, EINT11, CLKM1, I2S3_WS, USB_DRVVBUS_P0, PWM5, IRDA_TXD, USB_DRVVBUS_P1, DBG_MON_B_30),
- PINMUX_CONSTANTS(12, EINT12, CLKM2, I2S3_BCK, SRCLKENA0, RES4, I2S2_WS, RES6, DBG_MON_B_32),
- PINMUX_CONSTANTS(13, EINT13, CLKM3, I2S3_MCK, SRCLKENA0, RES4, I2S2_BCK, RES6, DBG_MON_A_32),
- PINMUX_CONSTANTS(14, EINT14, CMDAT0, CMCSD0, RES3, CLKM2, RES5, RES6, DBG_MON_B_6),
- PINMUX_CONSTANTS(15, EINT15, CMDAT1, CMCSD1, CMFLASH, CLKM3, RES5, RES6, DBG_MON_B_29),
- PINMUX_CONSTANTS(16, IDDIG, IDDIG, CMFLASH, RES3, PWM5, RES5, RES6, RES7),
- PINMUX_CONSTANTS(17, WATCHDOG, WATCHDOG_AO, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(18, CEC, CEC, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(19, HDMISCK, HDMISCK, HDCP_SCL, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(20, HDMISD, HDMISD, HDCP_SDA, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(21, HTPLG, HTPLG, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(22, MSDC3_DAT0, MSDC3_DAT0, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(23, MSDC3_DAT1, MSDC3_DAT1, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(24, MSDC3_DAT2, MSDC3_DAT2, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(25, MSDC3_DAT3, MSDC3_DAT3, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(26, MSDC3_CLK, MSDC3_CLK, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(27, MSDC3_CMD, MSDC3_CMD, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(28, MSDC3_DSL, MSDC3_DSL, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(29, UCTS2, UCTS2, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(30, URTS2, URTS2, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(31, URXD2, URXD2, UTXD2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(32, UTXD2, UTXD2, URXD2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(33, DAICLK, MRG_CLK, PCM0_CLK, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(34, DAIPCMIN, MRG_DI, PCM0_DI, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(35, DAIPCMOUT, MRG_DO, PCM0_DO, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(36, DAISYNC, MRG_SYNC, PCM0_SYNC, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(37, EINT16, USB_DRVVBUS_P0, USB_DRVVBUS_P1, PWM0, PWM1, PWM2, CLKM0, RES7),
- PINMUX_CONSTANTS(38, CONN_RST, USB_DRVVBUS_P0, USB_DRVVBUS_P1, RES3, RES4, RES5, CLKM1, RES7),
- PINMUX_CONSTANTS(39, CM2MCLK, CM2MCLK, CMCSD0, RES3, RES4, RES5, RES6, DBG_MON_A_17),
- PINMUX_CONSTANTS(40, CMPCLK, CMPCLK, CMCSK, CMCSD2, RES4, RES5, RES6, DBG_MON_A_18),
- PINMUX_CONSTANTS(41, CMMCLK, CMMCLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_19),
- PINMUX_CONSTANTS(42, DSI_TE, DSI_TE, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(43, SDA2, SDA2, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(44, SCL2, SCL2, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(45, SDA0, SDA0, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(46, SCL0, SCL0, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(47, RDN0_A, CMDAT2, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(48, RDP0_A, CMDAT3, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(49, RDN1_A, CMDAT4, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(50, RDP1_A, CMDAT5, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(51, RCN_A, CMDAT6, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(52, RCP_A, CMDAT7, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(53, RDN2_A, CMDAT8, CMCSD3, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(54, RDP2_A, CMDAT9, CMCSD2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(55, RDN3_A, CMHSYNC, CMCSD1, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(56, RDP3_A, CMVSYNC, CMCSD0, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(57, MSDC0_DAT0, MSDC0_DAT0, I2S1_WS, RES3, RES4, RES5, RES6, DBG_MON_B_7),
- PINMUX_CONSTANTS(58, MSDC0_DAT1, MSDC0_DAT1, I2S1_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_8),
- PINMUX_CONSTANTS(59, MSDC0_DAT2, MSDC0_DAT2, I2S1_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_9),
- PINMUX_CONSTANTS(60, MSDC0_DAT3, MSDC0_DAT3, I2S1_DO_1, RES3, RES4, RES5, RES6, DBG_MON_B_10),
- PINMUX_CONSTANTS(61, MSDC0_DAT4, MSDC0_DAT4, I2S1_DO_2, RES3, RES4, RES5, RES6, DBG_MON_B_11),
- PINMUX_CONSTANTS(62, MSDC0_DAT5, MSDC0_DAT5, I2S2_WS, RES3, RES4, RES5, RES6, DBG_MON_B_12),
- PINMUX_CONSTANTS(63, MSDC0_DAT6, MSDC0_DAT6, I2S2_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_13),
- PINMUX_CONSTANTS(64, MSDC0_DAT7, MSDC0_DAT7, I2S2_DI_1, RES3, RES4, RES5, RES6, DBG_MON_B_14),
- PINMUX_CONSTANTS(65, MSDC0_CLK, MSDC0_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_16),
- PINMUX_CONSTANTS(66, MSDC0_CMD, MSDC0_CMD, I2S2_DI_2, RES3, RES4, RES5, RES6, DBG_MON_B_15),
- PINMUX_CONSTANTS(67, MSDC0_DSL, MSDC0_DSL, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_17),
- PINMUX_CONSTANTS(68, MSDC0_RST, MSDC0_RSTB, I2S2_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_18),
- PINMUX_CONSTANTS(69, SPI_CK, SPI_CK_0, I2S3_DO_1, PWM0, PWM5, I2S2_MCK, RES6, DBG_MON_B_19),
- PINMUX_CONSTANTS(70, SPI_MI, SPI_MI_0, I2S3_DO_2, PWM1, SPI_MO_0, I2S2_DI_1, DSI1_TE, DBG_MON_B_20),
- PINMUX_CONSTANTS(71, SPI_MO, SPI_MO_0, I2S3_DO_3, PWM2, SPI_MI_0, I2S2_DI_2, RES6, DBG_MON_B_21),
- PINMUX_CONSTANTS(72, SPI_CS, SPI_CS_0, I2S3_DO_4, PWM3, PWM6, DISP_PWM1, RES6, DBG_MON_B_22),
- PINMUX_CONSTANTS(73, MSDC1_DAT0, MSDC1_DAT0, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_24),
- PINMUX_CONSTANTS(74, MSDC1_DAT1, MSDC1_DAT1, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_25),
- PINMUX_CONSTANTS(75, MSDC1_DAT2, MSDC1_DAT2, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_26),
- PINMUX_CONSTANTS(76, MSDC1_DAT3, MSDC1_DAT3, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_27),
- PINMUX_CONSTANTS(77, MSDC1_CLK, MSDC1_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_28),
- PINMUX_CONSTANTS(78, MSDC1_CMD, MSDC1_CMD, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_23),
- PINMUX_CONSTANTS(79, PWRAP_SPI0_MI, PWRAP_SPIMI, PWRAP_SPIMO, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(80, PWRAP_SPI0_MO, PWRAP_SPIMO, PWRAP_SPIMI, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(81, PWRAP_SPI0_CK, PWRAP_SPICK, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(82, PWRAP_SPI0_CSN, PWRAP_SPICS, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(83, AUD_CLK_MOSI, AUD_CLK_MOSI, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(84, AUD_DAT_MISO, AUD_DAT_MISO, AUD_DAT_MOSI, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(85, AUD_DAT_MOSI, AUD_DAT_MOSI, AUD_DAT_MISO, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(86, RTC32K_CK, RTC32K_CK, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(87, DISP_PWM0, DISP_PWM0, DISP_PWM1, RES3, RES4, RES5, RES6, DBG_MON_B_31),
- PINMUX_CONSTANTS(88, SRCLKENAI, SRCLKENAI, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(89, SRCLKENAI2, SRCLKENAI2, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(90, SRCLKENA0, SRCLKENA0, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(91, SRCLKENA1, SRCLKENA1, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(92, PCM_CLK, PCM1_CLK, I2S0_BCK, RES3, RES4, RES5, RES6, DBG_MON_A_24),
- PINMUX_CONSTANTS(93, PCM_SYNC, PCM1_SYNC, I2S0_WS, RES3, RES4, RES5, RES6, DBG_MON_A_25),
- PINMUX_CONSTANTS(94, PCM_RX, PCM1_DI, I2S0_DI, RES3, RES4, RES5, RES6, DBG_MON_A_26),
- PINMUX_CONSTANTS(95, PCM_TX, PCM1_DO, I2S0_DO, RES3, RES4, RES5, RES6, DBG_MON_A_27),
- PINMUX_CONSTANTS(96, URXD1, URXD1, UTXD1, RES3, RES4, RES5, RES6, DBG_MON_A_28),
- PINMUX_CONSTANTS(97, UTXD1, UTXD1, URXD1, RES3, RES4, RES5, RES6, DBG_MON_A_29),
- PINMUX_CONSTANTS(98, URTS1, URTS1, UCTS1, RES3, RES4, RES5, RES6, DBG_MON_A_30),
- PINMUX_CONSTANTS(99, UCTS1, UCTS1, URTS1, RES3, RES4, RES5, RES6, DBG_MON_A_31),
- PINMUX_CONSTANTS(100, MSDC2_DAT0, MSDC2_DAT0, RES2, USB_DRVVBUS_P0, SDA5, USB_DRVVBUS_P1, RES6, DBG_MON_B_0),
- PINMUX_CONSTANTS(101, MSDC2_DAT1, MSDC2_DAT1, RES2, AUD_SPDIF, SCL5, RES5, RES6, DBG_MON_B_1),
- PINMUX_CONSTANTS(102, MSDC2_DAT2, MSDC2_DAT2, RES2, UTXD0, RES4, PWM0, SPI_CK_1, DBG_MON_B_2),
- PINMUX_CONSTANTS(103, MSDC2_DAT3, MSDC2_DAT3, RES2, URXD0, RES4, PWM1, SPI_MI_1, DBG_MON_B_3),
- PINMUX_CONSTANTS(104, MSDC2_CLK, MSDC2_CLK, RES2, UTXD3, SDA3, PWM2, SPI_MO_1, DBG_MON_B_4),
- PINMUX_CONSTANTS(105, MSDC2_CMD, MSDC2_CMD, RES2, URXD3, SCL3, PWM3, SPI_CS_1, DBG_MON_B_5),
- PINMUX_CONSTANTS(106, SDA3, SDA3, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(107, SCL3, SCL3, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(108, JTMS, JTMS, MFG_JTAG_TMS, RES3, RES4, AP_MD32_JTAG_TMS, DFD_TMS, RES7),
- PINMUX_CONSTANTS(109, JTCK, JTCK, MFG_JTAG_TCK, RES3, RES4, AP_MD32_JTAG_TCK, DFD_TCK, RES7),
- PINMUX_CONSTANTS(110, JTDI, JTDI, MFG_JTAG_TDI, RES3, RES4, AP_MD32_JTAG_TDI, DFD_TDI, RES7),
- PINMUX_CONSTANTS(111, JTDO, JTDO, MFG_JTAG_TDO, RES3, RES4, AP_MD32_JTAG_TDO, DFD_TDO, RES7),
- PINMUX_CONSTANTS(112, JTRST_B, JTRST_B, MFG_JTAG_TRSTN, RES3, RES4, AP_MD32_JTAG_TRST, DFD_NTRST, RES7),
- PINMUX_CONSTANTS(113, URXD0, URXD0, UTXD0, RES3, RES4, RES5, I2S2_WS, DBG_MON_A_0),
- PINMUX_CONSTANTS(114, UTXD0, UTXD0, URXD0, RES3, RES4, RES5, I2S2_BCK, DBG_MON_A_1),
- PINMUX_CONSTANTS(115, URTS0, URTS0, UCTS0, RES3, RES4, RES5, I2S2_MCK, DBG_MON_A_2),
- PINMUX_CONSTANTS(116, UCTS0, UCTS0, URTS0, RES3, RES4, RES5, I2S2_DI_1, DBG_MON_A_3),
- PINMUX_CONSTANTS(117, URXD3, URXD3, UTXD3, RES3, RES4, RES5, RES6, DBG_MON_A_9),
- PINMUX_CONSTANTS(118, UTXD3, UTXD3, URXD3, RES3, RES4, RES5, RES6, DBG_MON_A_10),
- PINMUX_CONSTANTS(119, KPROW0, KROW0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_11),
- PINMUX_CONSTANTS(120, KPROW1, KROW1, RES2, PWM6, RES4, RES5, RES6, DBG_MON_A_12),
- PINMUX_CONSTANTS(121, KPROW2, KROW2, IRDA_PDN, USB_DRVVBUS_P0, PWM4, USB_DRVVBUS_P1, RES6, DBG_MON_A_13),
- PINMUX_CONSTANTS(122, KPCOL0, KCOL0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_14),
- PINMUX_CONSTANTS(123, KPCOL1, KCOL1, IRDA_RXD, PWM5, RES4, RES5, RES6, DBG_MON_A_15),
- PINMUX_CONSTANTS(124, KPCOL2, KCOL2, IRDA_TXD, USB_DRVVBUS_P0, PWM3, USB_DRVVBUS_P1, RES6, DBG_MON_A_16),
- PINMUX_CONSTANTS(125, SDA1, SDA1, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(126, SCL1, SCL1, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(127, LCM_RST, LCM_RST, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(128, I2S0_LRCK, I2S0_WS, I2S1_WS, I2S2_WS, RES4, SPI_CK_2, RES6, DBG_MON_A_4),
- PINMUX_CONSTANTS(129, I2S0_BCK, I2S0_BCK, I2S1_BCK, I2S2_BCK, RES4, SPI_MI_2, RES6, DBG_MON_A_5),
- PINMUX_CONSTANTS(130, I2S0_MCK, I2S0_MCK, I2S1_MCK, I2S2_MCK, RES4, SPI_MO_2, RES6, DBG_MON_A_6),
- PINMUX_CONSTANTS(131, I2S0_DATA0, I2S0_DO, I2S1_DO_1, I2S2_DI_1, RES4, SPI_CS_2, RES6, DBG_MON_A_7),
- PINMUX_CONSTANTS(132, I2S0_DATA1, I2S0_DI, I2S1_DO_2, I2S2_DI_2, RES4, RES5, RES6, DBG_MON_A_8),
- PINMUX_CONSTANTS(133, SDA4, SDA4, RES2, RES3, RES4, RES5, RES6, RES7),
- PINMUX_CONSTANTS(134, SCL4, SCL4, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_0, EINT0, IRDA_PDN, I2S1_WS, AUD_SPDIF, UTXD0, RES5, RES6, DBG_MON_A_20),
+ PINMUX_CONSTANTS(GPIO_PAD_1, EINT1, IRDA_RXD, I2S1_BCK, SDA5, URXD0, RES5, RES6, DBG_MON_A_21),
+ PINMUX_CONSTANTS(GPIO_PAD_2, EINT2, IRDA_TXD, I2S1_MCK, SCL5, UTXD3, RES5, RES6, DBG_MON_A_22),
+ PINMUX_CONSTANTS(GPIO_PAD_3, EINT3, DSI1_TE, I2S1_DO_1, SDA3, URXD3, RES5, RES6, DBG_MON_A_23),
+ PINMUX_CONSTANTS(GPIO_PAD_4, EINT4, DISP_PWM1, I2S1_DO_2, SCL3, UCTS3, RES5, SFWP_B, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_5, EINT5, PCM1_CLK, I2S2_WS, SPI_CK_3, URTS3, AP_MD32_JTAG_TMS, SFOUT, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_6, EINT6, PCM1_SYNC, I2S2_BCK, SPI_MI_3, RES4, AP_MD32_JTAG_TCK, SFCS0, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_7, EINT7, PCM1_DI, I2S2_DI_1, SPI_MO_3, RES4, AP_MD32_JTAG_TDI, SFHOLD, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_8, EINT8, PCM1_DO, I2S2_DI_2, SPI_CS_3, AUD_SPDIF, AP_MD32_JTAG_TDO, SFIN, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_9, EINT9, USB_DRVVBUS_P0, I2S2_MCK, RES3, USB_DRVVBUS_P1, AP_MD32_JTAG_TRST, SFCK, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_10, EINT10, CLKM0, DSI1_TE, DISP_PWM1, PWM4, IRDA_RXD, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_11, EINT11, CLKM1, I2S3_WS, USB_DRVVBUS_P0, PWM5, IRDA_TXD, USB_DRVVBUS_P1, DBG_MON_B_30),
+ PINMUX_CONSTANTS(GPIO_PAD_12, EINT12, CLKM2, I2S3_BCK, SRCLKENA0, RES4, I2S2_WS, RES6, DBG_MON_B_32),
+ PINMUX_CONSTANTS(GPIO_PAD_13, EINT13, CLKM3, I2S3_MCK, SRCLKENA0, RES4, I2S2_BCK, RES6, DBG_MON_A_32),
+ PINMUX_CONSTANTS(GPIO_PAD_14, EINT14, CMDAT0, CMCSD0, RES3, CLKM2, RES5, RES6, DBG_MON_B_6),
+ PINMUX_CONSTANTS(GPIO_PAD_15, EINT15, CMDAT1, CMCSD1, CMFLASH, CLKM3, RES5, RES6, DBG_MON_B_29),
+ PINMUX_CONSTANTS(GPIO_PAD_16, IDDIG, IDDIG, CMFLASH, RES3, PWM5, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_17, WATCHDOG, WATCHDOG_AO, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_18, CEC, CEC, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_19, HDMISCK, HDMISCK, HDCP_SCL, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_20, HDMISD, HDMISD, HDCP_SDA, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_21, HTPLG, HTPLG, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_22, MSDC3_DAT0, MSDC3_DAT0, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_23, MSDC3_DAT1, MSDC3_DAT1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_24, MSDC3_DAT2, MSDC3_DAT2, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_25, MSDC3_DAT3, MSDC3_DAT3, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_26, MSDC3_CLK, MSDC3_CLK, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_27, MSDC3_CMD, MSDC3_CMD, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_28, MSDC3_DSL, MSDC3_DSL, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_29, UCTS2, UCTS2, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_30, URTS2, URTS2, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_31, URXD2, URXD2, UTXD2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_32, UTXD2, UTXD2, URXD2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_33, DAICLK, MRG_CLK, PCM0_CLK, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_34, DAIPCMIN, MRG_DI, PCM0_DI, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_35, DAIPCMOUT, MRG_DO, PCM0_DO, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_36, DAISYNC, MRG_SYNC, PCM0_SYNC, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_37, EINT16, USB_DRVVBUS_P0, USB_DRVVBUS_P1, PWM0, PWM1, PWM2, CLKM0, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_38, CONN_RST, USB_DRVVBUS_P0, USB_DRVVBUS_P1, RES3, RES4, RES5, CLKM1, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_39, CM2MCLK, CM2MCLK, CMCSD0, RES3, RES4, RES5, RES6, DBG_MON_A_17),
+ PINMUX_CONSTANTS(GPIO_PAD_40, CMPCLK, CMPCLK, CMCSK, CMCSD2, RES4, RES5, RES6, DBG_MON_A_18),
+ PINMUX_CONSTANTS(GPIO_PAD_41, CMMCLK, CMMCLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_19),
+ PINMUX_CONSTANTS(GPIO_PAD_42, DSI_TE, DSI_TE, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_43, SDA2, SDA2, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_44, SCL2, SCL2, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_45, SDA0, SDA0, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_46, SCL0, SCL0, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_47, RDN0_A, CMDAT2, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_48, RDP0_A, CMDAT3, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_49, RDN1_A, CMDAT4, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_50, RDP1_A, CMDAT5, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_51, RCN_A, CMDAT6, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_52, RCP_A, CMDAT7, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_53, RDN2_A, CMDAT8, CMCSD3, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_54, RDP2_A, CMDAT9, CMCSD2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_55, RDN3_A, CMHSYNC, CMCSD1, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_56, RDP3_A, CMVSYNC, CMCSD0, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_57, MSDC0_DAT0, MSDC0_DAT0, I2S1_WS, RES3, RES4, RES5, RES6, DBG_MON_B_7),
+ PINMUX_CONSTANTS(GPIO_PAD_58, MSDC0_DAT1, MSDC0_DAT1, I2S1_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_8),
+ PINMUX_CONSTANTS(GPIO_PAD_59, MSDC0_DAT2, MSDC0_DAT2, I2S1_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_9),
+ PINMUX_CONSTANTS(GPIO_PAD_60, MSDC0_DAT3, MSDC0_DAT3, I2S1_DO_1, RES3, RES4, RES5, RES6, DBG_MON_B_10),
+ PINMUX_CONSTANTS(GPIO_PAD_61, MSDC0_DAT4, MSDC0_DAT4, I2S1_DO_2, RES3, RES4, RES5, RES6, DBG_MON_B_11),
+ PINMUX_CONSTANTS(GPIO_PAD_62, MSDC0_DAT5, MSDC0_DAT5, I2S2_WS, RES3, RES4, RES5, RES6, DBG_MON_B_12),
+ PINMUX_CONSTANTS(GPIO_PAD_63, MSDC0_DAT6, MSDC0_DAT6, I2S2_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_13),
+ PINMUX_CONSTANTS(GPIO_PAD_64, MSDC0_DAT7, MSDC0_DAT7, I2S2_DI_1, RES3, RES4, RES5, RES6, DBG_MON_B_14),
+ PINMUX_CONSTANTS(GPIO_PAD_65, MSDC0_CLK, MSDC0_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_16),
+ PINMUX_CONSTANTS(GPIO_PAD_66, MSDC0_CMD, MSDC0_CMD, I2S2_DI_2, RES3, RES4, RES5, RES6, DBG_MON_B_15),
+ PINMUX_CONSTANTS(GPIO_PAD_67, MSDC0_DSL, MSDC0_DSL, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_17),
+ PINMUX_CONSTANTS(GPIO_PAD_68, MSDC0_RST, MSDC0_RSTB, I2S2_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_18),
+ PINMUX_CONSTANTS(GPIO_PAD_69, SPI_CK, SPI_CK_0, I2S3_DO_1, PWM0, PWM5, I2S2_MCK, RES6, DBG_MON_B_19),
+ PINMUX_CONSTANTS(GPIO_PAD_70, SPI_MI, SPI_MI_0, I2S3_DO_2, PWM1, SPI_MO_0, I2S2_DI_1, DSI1_TE, DBG_MON_B_20),
+ PINMUX_CONSTANTS(GPIO_PAD_71, SPI_MO, SPI_MO_0, I2S3_DO_3, PWM2, SPI_MI_0, I2S2_DI_2, RES6, DBG_MON_B_21),
+ PINMUX_CONSTANTS(GPIO_PAD_72, SPI_CS, SPI_CS_0, I2S3_DO_4, PWM3, PWM6, DISP_PWM1, RES6, DBG_MON_B_22),
+ PINMUX_CONSTANTS(GPIO_PAD_73, MSDC1_DAT0, MSDC1_DAT0, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_24),
+ PINMUX_CONSTANTS(GPIO_PAD_74, MSDC1_DAT1, MSDC1_DAT1, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_25),
+ PINMUX_CONSTANTS(GPIO_PAD_75, MSDC1_DAT2, MSDC1_DAT2, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_26),
+ PINMUX_CONSTANTS(GPIO_PAD_76, MSDC1_DAT3, MSDC1_DAT3, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_27),
+ PINMUX_CONSTANTS(GPIO_PAD_77, MSDC1_CLK, MSDC1_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_28),
+ PINMUX_CONSTANTS(GPIO_PAD_78, MSDC1_CMD, MSDC1_CMD, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_23),
+ PINMUX_CONSTANTS(GPIO_PAD_79, PWRAP_SPI0_MI, PWRAP_SPIMI, PWRAP_SPIMO, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_80, PWRAP_SPI0_MO, PWRAP_SPIMO, PWRAP_SPIMI, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_81, PWRAP_SPI0_CK, PWRAP_SPICK, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_82, PWRAP_SPI0_CSN, PWRAP_SPICS, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_83, AUD_CLK_MOSI, AUD_CLK_MOSI, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_84, AUD_DAT_MISO, AUD_DAT_MISO, AUD_DAT_MOSI, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_85, AUD_DAT_MOSI, AUD_DAT_MOSI, AUD_DAT_MISO, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_86, RTC32K_CK, RTC32K_CK, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_87, DISP_PWM0, DISP_PWM0, DISP_PWM1, RES3, RES4, RES5, RES6, DBG_MON_B_31),
+ PINMUX_CONSTANTS(GPIO_PAD_88, SRCLKENAI, SRCLKENAI, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_89, SRCLKENAI2, SRCLKENAI2, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_90, SRCLKENA0, SRCLKENA0, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_91, SRCLKENA1, SRCLKENA1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_92, PCM_CLK, PCM1_CLK, I2S0_BCK, RES3, RES4, RES5, RES6, DBG_MON_A_24),
+ PINMUX_CONSTANTS(GPIO_PAD_93, PCM_SYNC, PCM1_SYNC, I2S0_WS, RES3, RES4, RES5, RES6, DBG_MON_A_25),
+ PINMUX_CONSTANTS(GPIO_PAD_94, PCM_RX, PCM1_DI, I2S0_DI, RES3, RES4, RES5, RES6, DBG_MON_A_26),
+ PINMUX_CONSTANTS(GPIO_PAD_95, PCM_TX, PCM1_DO, I2S0_DO, RES3, RES4, RES5, RES6, DBG_MON_A_27),
+ PINMUX_CONSTANTS(GPIO_PAD_96, URXD1, URXD1, UTXD1, RES3, RES4, RES5, RES6, DBG_MON_A_28),
+ PINMUX_CONSTANTS(GPIO_PAD_97, UTXD1, UTXD1, URXD1, RES3, RES4, RES5, RES6, DBG_MON_A_29),
+ PINMUX_CONSTANTS(GPIO_PAD_98, URTS1, URTS1, UCTS1, RES3, RES4, RES5, RES6, DBG_MON_A_30),
+ PINMUX_CONSTANTS(GPIO_PAD_99, UCTS1, UCTS1, URTS1, RES3, RES4, RES5, RES6, DBG_MON_A_31),
+ PINMUX_CONSTANTS(GPIO_PAD_100, MSDC2_DAT0, MSDC2_DAT0, RES2, USB_DRVVBUS_P0, SDA5, USB_DRVVBUS_P1, RES6, DBG_MON_B_0),
+ PINMUX_CONSTANTS(GPIO_PAD_101, MSDC2_DAT1, MSDC2_DAT1, RES2, AUD_SPDIF, SCL5, RES5, RES6, DBG_MON_B_1),
+ PINMUX_CONSTANTS(GPIO_PAD_102, MSDC2_DAT2, MSDC2_DAT2, RES2, UTXD0, RES4, PWM0, SPI_CK_1, DBG_MON_B_2),
+ PINMUX_CONSTANTS(GPIO_PAD_103, MSDC2_DAT3, MSDC2_DAT3, RES2, URXD0, RES4, PWM1, SPI_MI_1, DBG_MON_B_3),
+ PINMUX_CONSTANTS(GPIO_PAD_104, MSDC2_CLK, MSDC2_CLK, RES2, UTXD3, SDA3, PWM2, SPI_MO_1, DBG_MON_B_4),
+ PINMUX_CONSTANTS(GPIO_PAD_105, MSDC2_CMD, MSDC2_CMD, RES2, URXD3, SCL3, PWM3, SPI_CS_1, DBG_MON_B_5),
+ PINMUX_CONSTANTS(GPIO_PAD_106, SDA3, SDA3, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_107, SCL3, SCL3, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_108, JTMS, JTMS, MFG_JTAG_TMS, RES3, RES4, AP_MD32_JTAG_TMS, DFD_TMS, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_109, JTCK, JTCK, MFG_JTAG_TCK, RES3, RES4, AP_MD32_JTAG_TCK, DFD_TCK, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_110, JTDI, JTDI, MFG_JTAG_TDI, RES3, RES4, AP_MD32_JTAG_TDI, DFD_TDI, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_111, JTDO, JTDO, MFG_JTAG_TDO, RES3, RES4, AP_MD32_JTAG_TDO, DFD_TDO, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_112, JTRST_B, JTRST_B, MFG_JTAG_TRSTN, RES3, RES4, AP_MD32_JTAG_TRST, DFD_NTRST, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_113, URXD0, URXD0, UTXD0, RES3, RES4, RES5, I2S2_WS, DBG_MON_A_0),
+ PINMUX_CONSTANTS(GPIO_PAD_114, UTXD0, UTXD0, URXD0, RES3, RES4, RES5, I2S2_BCK, DBG_MON_A_1),
+ PINMUX_CONSTANTS(GPIO_PAD_115, URTS0, URTS0, UCTS0, RES3, RES4, RES5, I2S2_MCK, DBG_MON_A_2),
+ PINMUX_CONSTANTS(GPIO_PAD_116, UCTS0, UCTS0, URTS0, RES3, RES4, RES5, I2S2_DI_1, DBG_MON_A_3),
+ PINMUX_CONSTANTS(GPIO_PAD_117, URXD3, URXD3, UTXD3, RES3, RES4, RES5, RES6, DBG_MON_A_9),
+ PINMUX_CONSTANTS(GPIO_PAD_118, UTXD3, UTXD3, URXD3, RES3, RES4, RES5, RES6, DBG_MON_A_10),
+ PINMUX_CONSTANTS(GPIO_PAD_119, KPROW0, KROW0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_11),
+ PINMUX_CONSTANTS(GPIO_PAD_120, KPROW1, KROW1, RES2, PWM6, RES4, RES5, RES6, DBG_MON_A_12),
+ PINMUX_CONSTANTS(GPIO_PAD_121, KPROW2, KROW2, IRDA_PDN, USB_DRVVBUS_P0, PWM4, USB_DRVVBUS_P1, RES6, DBG_MON_A_13),
+ PINMUX_CONSTANTS(GPIO_PAD_122, KPCOL0, KCOL0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_14),
+ PINMUX_CONSTANTS(GPIO_PAD_123, KPCOL1, KCOL1, IRDA_RXD, PWM5, RES4, RES5, RES6, DBG_MON_A_15),
+ PINMUX_CONSTANTS(GPIO_PAD_124, KPCOL2, KCOL2, IRDA_TXD, USB_DRVVBUS_P0, PWM3, USB_DRVVBUS_P1, RES6, DBG_MON_A_16),
+ PINMUX_CONSTANTS(GPIO_PAD_125, SDA1, SDA1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_126, SCL1, SCL1, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_127, LCM_RST, LCM_RST, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_128, I2S0_LRCK, I2S0_WS, I2S1_WS, I2S2_WS, RES4, SPI_CK_2, RES6, DBG_MON_A_4),
+ PINMUX_CONSTANTS(GPIO_PAD_129, I2S0_BCK, I2S0_BCK, I2S1_BCK, I2S2_BCK, RES4, SPI_MI_2, RES6, DBG_MON_A_5),
+ PINMUX_CONSTANTS(GPIO_PAD_130, I2S0_MCK, I2S0_MCK, I2S1_MCK, I2S2_MCK, RES4, SPI_MO_2, RES6, DBG_MON_A_6),
+ PINMUX_CONSTANTS(GPIO_PAD_131, I2S0_DATA0, I2S0_DO, I2S1_DO_1, I2S2_DI_1, RES4, SPI_CS_2, RES6, DBG_MON_A_7),
+ PINMUX_CONSTANTS(GPIO_PAD_132, I2S0_DATA1, I2S0_DI, I2S1_DO_2, I2S2_DI_2, RES4, RES5, RES6, DBG_MON_A_8),
+ PINMUX_CONSTANTS(GPIO_PAD_133, SDA4, SDA4, RES2, RES3, RES4, RES5, RES6, RES7),
+ PINMUX_CONSTANTS(GPIO_PAD_134, SCL4, SCL4, RES2, RES3, RES4, RES5, RES6, RES7),
};
#endif /* SOC_MEDIATEK_MT8173_PINMUX_H */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0
Gerrit-Change-Number: 27416
Gerrit-PatchSet: 1
Gerrit-Owner: Tristan Hsieh <tristan.shieh at mediatek.com>
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