[coreboot-gerrit] Change in coreboot[master]: google/lars: Convert to a variant of glados
Matt DeVillier (Code Review)
gerrit at coreboot.org
Mon Jul 9 09:45:41 CEST 2018
Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27413
Change subject: google/lars: Convert to a variant of glados
......................................................................
google/lars: Convert to a variant of glados
Convert lars to a variant of glados Skylake reference board:
- add lars-specific DPTF, EC config, GPIO config, Kconfig,
NHLT config, PEI data, VBT, SPD data, and devicetree
- add conditional generation of NHLT ACPI data for Maxim codec,
including override of OEM ID and OEM table ID
- remove existing lars board/directory
Test: build/boot google/lars, verify functionality unchanged
from pre-variant configuration
Change-Id: Iab37f1b92b0f3a5d99796f916a6fdcc14ce4eef4
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/mainboard/google/glados/Kconfig
M src/mainboard/google/glados/Kconfig.name
M src/mainboard/google/glados/mainboard.c
R src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
R src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
R src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex
R src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex
R src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex
R src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex
R src/mainboard/google/glados/variants/lars/Makefile.inc
R src/mainboard/google/glados/variants/lars/data.vbt
R src/mainboard/google/glados/variants/lars/devicetree.cb
R src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl
R src/mainboard/google/glados/variants/lars/include/variant/acpi/mainboard.asl
R src/mainboard/google/glados/variants/lars/include/variant/ec.h
R src/mainboard/google/glados/variants/lars/include/variant/gpio.h
R src/mainboard/google/glados/variants/lars/variant.c
D src/mainboard/google/lars/Kconfig
D src/mainboard/google/lars/Kconfig.name
D src/mainboard/google/lars/Makefile.inc
D src/mainboard/google/lars/acpi/ec.asl
D src/mainboard/google/lars/acpi/superio.asl
D src/mainboard/google/lars/board_info.txt
D src/mainboard/google/lars/bootblock_mainboard.c
D src/mainboard/google/lars/chromeos.c
D src/mainboard/google/lars/chromeos.fmd
D src/mainboard/google/lars/cmos.layout
D src/mainboard/google/lars/dsdt.asl
D src/mainboard/google/lars/ec.c
D src/mainboard/google/lars/ec.h
D src/mainboard/google/lars/mainboard.c
D src/mainboard/google/lars/ramstage.c
D src/mainboard/google/lars/romstage.c
D src/mainboard/google/lars/smihandler.c
D src/mainboard/google/lars/spd/empty.spd.hex
D src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866.spd.hex
D src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866.spd.hex
D src/mainboard/google/lars/spd/spd.c
D src/mainboard/google/lars/spd/spd.h
39 files changed, 129 insertions(+), 1,124 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/27413/1
diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 9ef8736..99e538f 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -38,6 +38,7 @@
string
default "Chell" if BOARD_GOOGLE_CHELL
default "Glados" if BOARD_GOOGLE_GLADOS
+ default "Lars" if BOARD_GOOGLE_LARS
config MAINBOARD_FAMILY
string
@@ -47,11 +48,13 @@
string
default "chell" if BOARD_GOOGLE_CHELL
default "glados" if BOARD_GOOGLE_GLADOS
+ default "lars" if BOARD_GOOGLE_LARS
config DEVICETREE
string
default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL
default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS
+ default "variants/lars/devicetree.cb" if BOARD_GOOGLE_LARS
config MAX_CPUS
int
@@ -70,15 +73,18 @@
string
default "chell" if BOARD_GOOGLE_CHELL
default "glados" if BOARD_GOOGLE_GLADOS
+ default ""
config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
string
default "chell_pd" if BOARD_GOOGLE_CHELL
default "glados_pd" if BOARD_GOOGLE_GLADOS
+ default ""
config GBB_HWID
string
depends on CHROMEOS
default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL
default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
+ default "LARS TEST 5001" if BOARD_GOOGLE_LARS
endif
diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name
index 686107d..1bbeb3e 100644
--- a/src/mainboard/google/glados/Kconfig.name
+++ b/src/mainboard/google/glados/Kconfig.name
@@ -10,3 +10,10 @@
select BOARD_GOOGLE_BASEBOARD_GLADOS
select NHLT_DMIC_4CH
select NHLT_SSM4567
+
+config BOARD_GOOGLE_LARS
+ bool "-> Lars (Acer Chromebook 14 for Work (CP5-471))"
+ select BOARD_GOOGLE_BASEBOARD_GLADOS
+ select DRIVERS_GENERIC_MAX98357A
+ select EXCLUDE_NATIVE_SD_INTERFACE
+ select NHLT_MAX98357
diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c
index 921595e..451b3d4 100644
--- a/src/mainboard/google/glados/mainboard.c
+++ b/src/mainboard/google/glados/mainboard.c
@@ -24,6 +24,9 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
+static const char *oem_id_maxim = "INTEL";
+static const char *oem_table_id_maxim = "SCRDMAX";
+
static void mainboard_init(struct device *dev)
{
mainboard_ec_init();
@@ -35,6 +38,8 @@
uintptr_t start_addr;
uintptr_t end_addr;
struct nhlt *nhlt;
+ const char *oem_id = NULL;
+ const char *oem_table_id = NULL;
start_addr = current;
@@ -57,11 +62,21 @@
if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))
printk(BIOS_ERR, "Couldn't add ssm4567.\n");
+ /* MAXIM Smart Amps for left and right. */
+ if (IS_ENABLED(CONFIG_NHLT_MAX98357)) {
+ if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))
+ printk(BIOS_ERR, "Couldn't add max98357.\n");
+
+ oem_id = oem_id_maxim;
+ oem_table_id = oem_table_id_maxim;
+ }
+
/* NAU88l25 Headset codec. */
if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1))
printk(BIOS_ERR, "Couldn't add headset codec.\n");
- end_addr = nhlt_soc_serialize(nhlt, start_addr);
+ end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr,
+ oem_id, oem_table_id, 0);
if (end_addr != start_addr)
acpi_add_table(rsdp, (void *)start_addr);
diff --git a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
similarity index 100%
rename from src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
rename to src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
diff --git a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
similarity index 100%
rename from src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
rename to src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
diff --git a/src/mainboard/google/lars/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex b/src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex
similarity index 100%
rename from src/mainboard/google/lars/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex
rename to src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex
diff --git a/src/mainboard/google/lars/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex b/src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex
similarity index 100%
rename from src/mainboard/google/lars/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex
rename to src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex
diff --git a/src/mainboard/google/lars/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex
similarity index 100%
rename from src/mainboard/google/lars/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex
rename to src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex
diff --git a/src/mainboard/google/lars/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex
similarity index 100%
rename from src/mainboard/google/lars/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex
rename to src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex
diff --git a/src/mainboard/google/lars/spd/Makefile.inc b/src/mainboard/google/glados/variants/lars/Makefile.inc
similarity index 89%
rename from src/mainboard/google/lars/spd/Makefile.inc
rename to src/mainboard/google/glados/variants/lars/Makefile.inc
index fff5856..89360a7 100644
--- a/src/mainboard/google/lars/spd/Makefile.inc
+++ b/src/mainboard/google/glados/variants/lars/Makefile.inc
@@ -14,7 +14,8 @@
## GNU General Public License for more details.
##
-romstage-y += spd.c
+romstage-y += variant.c
+ramstage-y += variant.c
SPD_BIN = $(obj)/spd.bin
@@ -25,17 +26,16 @@
SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0100 Single Channel 4GB
SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b0101 Dual Channel 8GB
SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 # 0b0110 Dual Channel 4GB
-SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866 # 0b0111 Single Channel 4GB
+SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b0111 Single Channel 4GB
SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b1000 Dual Channel 4GB
SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107-2G-1866 # 0b1001 Dual Channel 8GB
-SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866 # 0b1010 Dual Channel 4GB
+SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR # 0b1010 Dual Channel 4GB
SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107-2G-1866 # 0b1011 Single Channel 4GB
SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b1100 Single Channel 4GB
-SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866 # 0b1101 Dual Channel 8GB
+SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b1101 Dual Channel 8GB
SPD_SOURCES += empty # 0b1110
SPD_SOURCES += empty # 0b1111
-
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
# Include spd ROM data
@@ -48,4 +48,4 @@
cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
+spd.bin-type := spd
\ No newline at end of file
diff --git a/src/mainboard/google/lars/data.vbt b/src/mainboard/google/glados/variants/lars/data.vbt
similarity index 100%
rename from src/mainboard/google/lars/data.vbt
rename to src/mainboard/google/glados/variants/lars/data.vbt
Binary files differ
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb
similarity index 75%
rename from src/mainboard/google/lars/devicetree.cb
rename to src/mainboard/google/glados/variants/lars/devicetree.cb
index 6bb460a..2eda59b 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/glados/variants/lars/devicetree.cb
@@ -36,6 +36,11 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
+ register "SerialIrqConfigSirqEnable" = "1"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "4" # 4s
+ register "PmConfigSlpSusMinAssert" = "3" # 4s
+ register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
register "pirqa_routing" = "PCH_IRQ11"
@@ -47,22 +52,6 @@
register "pirqg_routing" = "PCH_IRQ11"
register "pirqh_routing" = "PCH_IRQ11"
- # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
- # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
- register "PmConfigSlpS3MinAssert" = "0x02"
-
- # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
- register "PmConfigSlpS4MinAssert" = "0x04"
-
- # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
- register "PmConfigSlpSusMinAssert" = "0x03"
-
- # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
- register "PmConfigSlpAMinAssert" = "0x03"
-
- # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
- register "SerialIrqConfigSirqEnable" = "0x01"
-
# VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+
#| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
@@ -78,67 +67,68 @@
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-------+-------+-------------+-------------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x10, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x1C, \
- .voltage_limit = 0x5F0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(7),
+ .voltage_limit = 1520,
}"
register "domain_vr_config[VR_IA_CORE]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x88, \
- .voltage_limit = 0x5F0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
}"
+
register "domain_vr_config[VR_RING]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x88, \
- .voltage_limit = 0x5F0, \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x8C ,\
- .voltage_limit = 0x5F0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x8C, \
- .voltage_limit = 0x5F0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
}"
# Enable Root port 1.
@@ -163,18 +153,18 @@
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
- register "SerialIoDevMode" = "{ \
- [PchSerialIoIndexI2C0] = PchSerialIoPci, \
- [PchSerialIoIndexI2C1] = PchSerialIoPci, \
- [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C4] = PchSerialIoPci, \
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart0] = PchSerialIoPci, \
- [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart0] = PchSerialIoPci,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
# PL2 override 25W
diff --git a/src/mainboard/google/lars/acpi/dptf.asl b/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl
similarity index 97%
rename from src/mainboard/google/lars/acpi/dptf.asl
rename to src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl
index c85e1b6..1f464c5 100644
--- a/src/mainboard/google/lars/acpi/dptf.asl
+++ b/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl
@@ -132,6 +132,3 @@
1000 /* StepSize */
}
})
-
-/* Include DPTF */
-#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/lars/acpi_tables.c b/src/mainboard/google/glados/variants/lars/include/variant/acpi/mainboard.asl
similarity index 100%
rename from src/mainboard/google/lars/acpi_tables.c
rename to src/mainboard/google/glados/variants/lars/include/variant/acpi/mainboard.asl
diff --git a/src/mainboard/google/lars/acpi/mainboard.asl b/src/mainboard/google/glados/variants/lars/include/variant/ec.h
similarity index 72%
rename from src/mainboard/google/lars/acpi/mainboard.asl
rename to src/mainboard/google/glados/variants/lars/include/variant/ec.h
index 861d39f..3c094b5 100644
--- a/src/mainboard/google/lars/acpi/mainboard.asl
+++ b/src/mainboard/google/glados/variants/lars/include/variant/ec.h
@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,12 +13,8 @@
* GNU General Public License for more details.
*/
-#include "../gpio.h"
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
-Scope (\_SB)
-{
- Device (PWRB)
- {
- Name (_HID, EisaId ("PNP0C0C"))
- }
-}
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h
similarity index 100%
rename from src/mainboard/google/lars/gpio.h
rename to src/mainboard/google/glados/variants/lars/include/variant/gpio.h
diff --git a/src/mainboard/google/lars/pei_data.c b/src/mainboard/google/glados/variants/lars/variant.c
similarity index 72%
rename from src/mainboard/google/lars/pei_data.c
rename to src/mainboard/google/glados/variants/lars/variant.c
index 67d8644..297b149 100644
--- a/src/mainboard/google/lars/pei_data.c
+++ b/src/mainboard/google/glados/variants/lars/variant.c
@@ -16,14 +16,18 @@
#include <stdint.h>
#include <string.h>
+#include <baseboard/variant.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
-#include "boardid.h"
-/* PCH_MEM_CFG[3:0] */
-#define MAX_MEMORY_CONFIG 0x10
#define K4E6E304EB_MEM_ID 0x5
-#define RCOMP_TARGET_PARAMS 0x5
+
+#define MEM_SINGLE_CHAN0 0x0
+#define MEM_SINGLE_CHAN3 0x3
+#define MEM_SINGLE_CHAN4 0x4
+#define MEM_SINGLE_CHAN7 0x7
+#define MEM_SINGLE_CHANB 0xb
+#define MEM_SINGLE_CHANC 0xc
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
@@ -42,14 +46,10 @@
const u16 RcompResistor[3] = { 200, 81, 162 };
/* Rcomp target */
- static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
- 100, 40, 40, 23, 40
- };
+ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
/*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EB -EGCF*/
- static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = {
- 100, 40, 40, 21, 40
- };
+ const u16 StrengthendRcompTarget[5] = { 100, 40, 40, 21, 40 };
/* Default Rcomp Target assignment */
const u16 *targeted_rcomp = RcompTarget;
@@ -57,13 +57,22 @@
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
memcpy(pei_data->RcompResistor, RcompResistor,
- sizeof(RcompResistor));
+ sizeof(RcompResistor));
/* Override Rcomp Target assignment for specific SKU(s) */
if (pei_data->mem_cfg_id == K4E6E304EB_MEM_ID)
targeted_rcomp = StrengthendRcompTarget;
memcpy(pei_data->RcompTarget, targeted_rcomp,
- sizeof(pei_data->RcompTarget));
+ sizeof(pei_data->RcompTarget));
+}
+int is_dual_channel(const int spd_index)
+{
+ return (spd_index != MEM_SINGLE_CHAN0
+ && spd_index != MEM_SINGLE_CHAN3
+ && spd_index != MEM_SINGLE_CHAN4
+ && spd_index != MEM_SINGLE_CHAN7
+ && spd_index != MEM_SINGLE_CHANB
+ && spd_index != MEM_SINGLE_CHANC);
}
diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig
deleted file mode 100644
index 9f74fec..0000000
--- a/src/mainboard/google/lars/Kconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-if BOARD_GOOGLE_LARS
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ROMSIZE_KB_16384
- select DRIVERS_GENERIC_MAX98357A
- select DRIVERS_I2C_GENERIC
- select DRIVERS_I2C_NAU8825
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
- select EC_GOOGLE_CHROMEEC_BOARDID
- select EC_GOOGLE_CHROMEEC_LPC
- select EC_GOOGLE_CHROMEEC_MEC
- select EC_GOOGLE_CHROMEEC_PD
- select EXCLUDE_NATIVE_SD_INTERFACE
- select HAVE_ACPI_RESUME
- select HAVE_ACPI_TABLES
- select HAVE_OPTION_TABLE
- select HAVE_SMI_HANDLER
- select INTEL_GMA_HAVE_VBT
- select MAINBOARD_HAS_CHROMEOS
- select MAINBOARD_HAS_LPC_TPM
- select MAINBOARD_HAS_TPM1
- select SOC_INTEL_SKYLAKE
- select SYSTEM_TYPE_LAPTOP
-
-config VBOOT
- select EC_GOOGLE_CHROMEEC_SWITCHES
- select VBOOT_LID_SWITCH
-
-config IRQ_SLOT_COUNT
- int
- default 18
-
-config MAINBOARD_DIR
- string
- default "google/lars"
-
-config MAINBOARD_PART_NUMBER
- string
- default "Lars"
-
-config MAINBOARD_FAMILY
- string
- default "Google_Lars"
-
-config MAX_CPUS
- int
- default 8
-
-config TPM_PIRQ
- hex
- default 0x18 # GPP_E0_IRQ
-
-config INCLUDE_NHLT_BLOBS
- bool "Include blobs for audio."
- select NHLT_DMIC_2CH
- select NHLT_MAX98357
- select NHLT_NAU88L25
-
-config GBB_HWID
- string
- depends on CHROMEOS
- default "LARS TEST 5001"
-endif
diff --git a/src/mainboard/google/lars/Kconfig.name b/src/mainboard/google/lars/Kconfig.name
deleted file mode 100644
index 8ab4923..0000000
--- a/src/mainboard/google/lars/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_LARS
- bool "Lars (Acer Chromebook 14 for Work (CP5-471))"
diff --git a/src/mainboard/google/lars/Makefile.inc b/src/mainboard/google/lars/Makefile.inc
deleted file mode 100644
index c8480f3..0000000
--- a/src/mainboard/google/lars/Makefile.inc
+++ /dev/null
@@ -1,34 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 Google Inc.
-## Copyright (C) 2015 Intel Corporation.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-subdirs-y += spd
-
-bootblock-y += bootblock_mainboard.c
-
-romstage-y += pei_data.c
-
-bootblock-$(CONFIG_CHROMEOS) += chromeos.c
-verstage-$(CONFIG_CHROMEOS) += chromeos.c
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-
-ramstage-y += mainboard.c
-ramstage-y += pei_data.c
-ramstage-y += ramstage.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/google/lars/acpi/ec.asl b/src/mainboard/google/lars/acpi/ec.asl
deleted file mode 100644
index d90d87d..0000000
--- a/src/mainboard/google/lars/acpi/ec.asl
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include "../ec.h"
-#include "../gpio.h"
-
-/* Enable EC backed ALS device in ACPI */
-#define EC_ENABLE_ALS_DEVICE
-
-/* Enable EC backed Keyboard Backlight in ACPI */
-#define EC_ENABLE_KEYBOARD_BACKLIGHT
-
-/* Enable EC backed PD MCU device in ACPI */
-#define EC_ENABLE_PD_MCU_DEVICE
-
-/* Enable LID switch and provide wake pin for EC */
-#define EC_ENABLE_LID_SWITCH
-#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
-
-/* ACPI code for EC functions */
-#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/lars/acpi/superio.asl b/src/mainboard/google/lars/acpi/superio.asl
deleted file mode 100644
index 803d2e3..0000000
--- a/src/mainboard/google/lars/acpi/superio.asl
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include "../ec.h"
-
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
-#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
-
-/* ACPI code for EC SuperIO functions */
-#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/lars/board_info.txt b/src/mainboard/google/lars/board_info.txt
deleted file mode 100644
index 8547dda..0000000
--- a/src/mainboard/google/lars/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Google
-Board name: Lars Skylake chromebook
-Category: laptop
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/google/lars/bootblock_mainboard.c b/src/mainboard/google/lars/bootblock_mainboard.c
deleted file mode 100644
index 627b4e8..0000000
--- a/src/mainboard/google/lars/bootblock_mainboard.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <bootblock_common.h>
-#include <soc/gpio.h>
-#include "gpio.h"
-
-static void early_config_gpio(void)
-{
- /* This is a hack for FSP because it does things in MemoryInit()
- * which it shouldn't do. We have to prepare certain gpios here
- * because of the brokenness in FSP. */
- gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}
-
-void bootblock_mainboard_init(void)
-{
- early_config_gpio();
-}
diff --git a/src/mainboard/google/lars/chromeos.c b/src/mainboard/google/lars/chromeos.c
deleted file mode 100644
index 54f9bbe..0000000
--- a/src/mainboard/google/lars/chromeos.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <rules.h>
-#include <gpio.h>
-#include <soc/gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "gpio.h"
-
-#if ENV_RAMSTAGE
-#include <boot/coreboot_tables.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
- {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- {-1, ACTIVE_HIGH, 0, "power"},
- {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
- {GPIO_EC_IN_RW, ACTIVE_HIGH,
- gpio_get(GPIO_EC_IN_RW), "EC in RW"},
- };
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-#endif /* ENV_RAMSTAGE */
-
-int get_write_protect_state(void)
-{
- /* Read PCH_WP GPIO. */
- return gpio_get(GPIO_PCH_WP);
-}
-
-static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
-};
-
-void mainboard_chromeos_acpi_generate(void)
-{
- chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
-}
diff --git a/src/mainboard/google/lars/chromeos.fmd b/src/mainboard/google/lars/chromeos.fmd
deleted file mode 100644
index 58b6127..0000000
--- a/src/mainboard/google/lars/chromeos.fmd
+++ /dev/null
@@ -1,38 +0,0 @@
-FLASH at 0xff000000 0x1000000 {
- SI_ALL at 0x0 0x200000 {
- SI_DESC at 0x0 0x1000
- SI_ME at 0x1000 0x1ff000
- }
- SI_BIOS at 0x200000 0xe00000 {
- RW_SECTION_A at 0x0 0x3f0000 {
- VBLOCK_A at 0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0x3dffc0
- RW_FWID_A at 0x3effc0 0x40
- }
- RW_SECTION_B at 0x3f0000 0x3f0000 {
- VBLOCK_B at 0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0x3dffc0
- RW_FWID_B at 0x3effc0 0x40
- }
- RW_MRC_CACHE at 0x7e0000 0x10000
- RW_ELOG at 0x7f0000 0x4000
- RW_SHARED at 0x7f4000 0x4000 {
- SHARED_DATA at 0x0 0x2000
- VBLOCK_DEV at 0x2000 0x2000
- }
- RW_VPD at 0x7f8000 0x2000
- RW_NVRAM at 0x7fa000 0x6000
- RW_LEGACY(CBFS)@0x800000 0x200000
- WP_RO at 0xa00000 0x400000 {
- RO_VPD at 0x0 0x4000
- RO_UNUSED at 0x4000 0xc000
- RO_SECTION at 0x10000 0x3f0000 {
- FMAP at 0x0 0x800
- RO_FRID at 0x800 0x40
- RO_FRID_PAD at 0x840 0x7c0
- GBB at 0x1000 0xef000
- COREBOOT(CBFS)@0xf0000 0x300000
- }
- }
- }
-}
diff --git a/src/mainboard/google/lars/cmos.layout b/src/mainboard/google/lars/cmos.layout
deleted file mode 100644
index d032d60..0000000
--- a/src/mainboard/google/lars/cmos.layout
+++ /dev/null
@@ -1,125 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-## Copyright (C) 2015 Intel Corporation.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-# -----------------------------------------------------------------
-# Status Register A
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-# -----------------------------------------------------------------
-# Status Register B
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-# -----------------------------------------------------------------
-# Status Register C
-#96 4 r 0 status_c_rsvd
-#100 1 r 0 uf_flag
-#101 1 r 0 af_flag
-#102 1 r 0 pf_flag
-#103 1 r 0 irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104 7 r 0 status_d_rsvd
-#111 1 r 0 valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112 8 r 0 diag_rsvd1
-
-# -----------------------------------------------------------------
-0 120 r 0 reserved_memory
-#120 264 r 0 unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#390 2 r 0 unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392 3 r 0 unused
-395 4 e 6 debug_level
-#399 1 r 0 unused
-
-# coreboot config options: cpu
-400 1 e 2 hyper_threading
-#401 7 r 0 unused
-
-# coreboot config options: southbridge
-408 1 e 1 nmi
-409 2 e 7 power_on_after_fail
-#411 5 r 0 unused
-
-# coreboot config options: bootloader
-#Used by ChromeOS:
-416 128 r 0 vbnv
-#544 440 r 0 unused
-
-# SandyBridge MRC Scrambler Seed values
-896 32 r 0 mrc_scrambler_seed
-928 32 r 0 mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984 16 h 0 check_sum
-#1000 24 r 0 amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 0 Emergency
-6 1 Alert
-6 2 Critical
-6 3 Error
-6 4 Warning
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-7 0 Disable
-7 1 Enable
-7 2 Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/google/lars/dsdt.asl b/src/mainboard/google/lars/dsdt.asl
deleted file mode 100644
index b5a37c6..0000000
--- a/src/mainboard/google/lars/dsdt.asl
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x05, // DSDT revision: ACPI v5.0
- "COREv4", // OEM id
- "COREBOOT", // OEM table id
- 0x20110725 // OEM revision
-)
-{
- // Some generic macros
- #include <soc/intel/skylake/acpi/platform.asl>
-
- // global NVS and variables
- #include <soc/intel/skylake/acpi/globalnvs.asl>
-
- // CPU
- #include <soc/intel/skylake/acpi/cpu.asl>
-
- Scope (\_SB) {
- Device (PCI0)
- {
- #include <soc/intel/skylake/acpi/systemagent.asl>
- #include <soc/intel/skylake/acpi/pch.asl>
- }
-
- // Dynamic Platform Thermal Framework
- #include "acpi/dptf.asl"
- }
-
- // Chrome OS specific
- #include <vendorcode/google/chromeos/acpi/chromeos.asl>
-
- // Chipset specific sleep states
- #include <soc/intel/skylake/acpi/sleepstates.asl>
-
- // Mainboard specific
- #include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/google/lars/ec.c b/src/mainboard/google/lars/ec.c
deleted file mode 100644
index 3722378..0000000
--- a/src/mainboard/google/lars/ec.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include "ec.h"
-
-void mainboard_ec_init(void)
-{
- const struct google_chromeec_event_info info = {
- .log_events = MAINBOARD_EC_LOG_EVENTS,
- .sci_events = MAINBOARD_EC_SCI_EVENTS,
- .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
- .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
- };
-
- printk(BIOS_DEBUG, "mainboard: EC init\n");
-
- google_chromeec_events_init(&info, acpi_is_wakeup_s3());
-}
diff --git a/src/mainboard/google/lars/ec.h b/src/mainboard/google/lars/ec.h
deleted file mode 100644
index fcb0a70..0000000
--- a/src/mainboard/google/lars/ec.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_EC_H
-#define MAINBOARD_EC_H
-
-#include <ec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-
-#define MAINBOARD_EC_SCI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
-
-#define MAINBOARD_EC_SMI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
-
-/* EC can wake from S5 with lid or power button */
-#define MAINBOARD_EC_S5_WAKE_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/* EC can wake from S3 with lid or power button or key press */
-#define MAINBOARD_EC_S3_WAKE_EVENTS \
- (MAINBOARD_EC_S5_WAKE_EVENTS |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
-
-/* Log EC wake events plus EC shutdown events */
-#define MAINBOARD_EC_LOG_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
-
-#endif
diff --git a/src/mainboard/google/lars/mainboard.c b/src/mainboard/google/lars/mainboard.c
deleted file mode 100644
index 43895fb..0000000
--- a/src/mainboard/google/lars/mainboard.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <stdlib.h>
-#include <soc/nhlt.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include "ec.h"
-
-static void mainboard_init(struct device *dev)
-{
- mainboard_ec_init();
-}
-
-static unsigned long mainboard_write_acpi_tables(
- struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
-{
- uintptr_t start_addr;
- uintptr_t end_addr;
- struct nhlt *nhlt;
-
- start_addr = current;
-
- nhlt = nhlt_init();
-
- if (nhlt == NULL)
- return start_addr;
-
- /* 2 Channel DMIC array. */
- if (nhlt_soc_add_dmic_array(nhlt, 2))
- printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
-
- /* MAXIM Smart Amps for left and right. */
- if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))
- printk(BIOS_ERR, "Couldn't add max98357.\n");
-
- /* NAU88l25 Headset codec. */
- if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1))
- printk(BIOS_ERR, "Couldn't add headset codec.\n");
-
- end_addr = nhlt_soc_serialize(nhlt, start_addr);
-
- if (end_addr != start_addr)
- acpi_add_table(rsdp, (void *)start_addr);
-
- return end_addr;
-}
-
-/*
- * mainboard_enable is executed as first thing after
- * enumerate_buses().
- */
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->init = mainboard_init;
- dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
- dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/google/lars/ramstage.c b/src/mainboard/google/lars/ramstage.c
deleted file mode 100644
index 563c715..0000000
--- a/src/mainboard/google/lars/ramstage.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/ramstage.h>
-#include "gpio.h"
-
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
-{
- /* Configure pads prior to SiliconInit() in case there's any
- * dependencies during hardware initialization. */
- gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-}
diff --git a/src/mainboard/google/lars/romstage.c b/src/mainboard/google/lars/romstage.c
deleted file mode 100644
index b3ef0d8..0000000
--- a/src/mainboard/google/lars/romstage.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <gpio.h>
-#include <ec/google/chromeec/ec.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-#include <soc/romstage.h>
-#include "gpio.h"
-#include "spd/spd.h"
-
-void mainboard_romstage_entry(struct romstage_params *params)
-{
- /* PCH_MEM_CFG[3:0] */
- gpio_t spd_gpios[] = {
- GPIO_MEM_CONFIG_0,
- GPIO_MEM_CONFIG_1,
- GPIO_MEM_CONFIG_2,
- GPIO_MEM_CONFIG_3,
- };
-
- /* Turn on keyboard backlight to indicate we are booting */
- if (params->power_state->prev_sleep_state != ACPI_S3)
- google_chromeec_kbbacklight(25);
-
- params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios,
- ARRAY_SIZE(spd_gpios));
- /* Fill out PEI DATA */
- mainboard_fill_pei_data(params->pei_data);
- mainboard_fill_spd_data(params->pei_data);
- /* Initialize memory */
- romstage_common(params);
-}
-
-void mainboard_memory_init_params(struct romstage_params *params,
- MEMORY_INIT_UPD *memory_params)
-{
- if (params->pei_data->spd_data[0][0][0] != 0) {
- memory_params->MemorySpdPtr00 =
- (UINT32)(params->pei_data->spd_data[0][0]);
- memory_params->MemorySpdPtr10 =
- (UINT32)(params->pei_data->spd_data[1][0]);
- }
- memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
- sizeof(params->pei_data->dq_map[0]));
- memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],
- sizeof(params->pei_data->dq_map[1]));
- memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
- sizeof(params->pei_data->dqs_map[0]));
- memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
- sizeof(params->pei_data->dqs_map[1]));
- memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,
- sizeof(params->pei_data->RcompResistor));
- memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,
- sizeof(params->pei_data->RcompTarget));
- memory_params->MemorySpdDataLen = SPD_LEN;
- memory_params->DqPinsInterleaved = FALSE;
-}
diff --git a/src/mainboard/google/lars/smihandler.c b/src/mainboard/google/lars/smihandler.c
deleted file mode 100644
index 24a5b96..0000000
--- a/src/mainboard/google/lars/smihandler.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <elog.h>
-#include <ec/google/chromeec/smm.h>
-#include <soc/iomap.h>
-#include <soc/nvs.h>
-#include <soc/pm.h>
-#include <soc/smm.h>
-#include "ec.h"
-#include "gpio.h"
-
-int mainboard_io_trap_handler(int smif)
-{
- switch (smif) {
- case 0x99:
- printk(BIOS_DEBUG, "Sample\n");
- smm_get_gnvs()->smif = 0;
- break;
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- return 1;
-}
-
-void mainboard_smi_gpi_handler(const struct gpi_status *sts)
-{
- if (gpi_status_get(sts, EC_SMI_GPI))
- chromeec_smi_process_events();
-}
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
- chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
- MAINBOARD_EC_S5_WAKE_EVENTS);
-}
-
-int mainboard_smi_apmc(u8 apmc)
-{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
- chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
- MAINBOARD_EC_SMI_EVENTS);
- return 0;
-}
diff --git a/src/mainboard/google/lars/spd/empty.spd.hex b/src/mainboard/google/lars/spd/empty.spd.hex
deleted file mode 100644
index 9ec39f1..0000000
--- a/src/mainboard/google/lars/spd/empty.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866.spd.hex b/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866.spd.hex
deleted file mode 100644
index 5c1332e..0000000
--- a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-91 20 F1 03 05 19 05 03 03 11 01 08 09 00 40 05
-78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
-00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00
-48 39 43 43 4E 4E 4E 38 47 54 41 4C 41 52 2D 4E
-55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866.spd.hex b/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866.spd.hex
deleted file mode 100644
index 7c7c8d2..0000000
--- a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866.spd.hex
+++ /dev/null
@@ -1,16 +0,0 @@
-91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05
-78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
-00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00
-48 39 43 43 4E 4E 4E 42 4A 54 41 4C 41 52 2D 4E
-55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/lars/spd/spd.c b/src/mainboard/google/lars/spd/spd.c
deleted file mode 100644
index d9fe579..0000000
--- a/src/mainboard/google/lars/spd/spd.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/byteorder.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <string.h>
-
-#include "spd.h"
-
-static void mainboard_print_spd_info(uint8_t spd[])
-{
- const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
- const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
- const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
- const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
- const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
- const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- char spd_name[SPD_PART_LEN+1] = { 0 };
-
- int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
- int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
- int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
- int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
- int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
- int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
- int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
-
- /* Module type */
- printk(BIOS_INFO, "SPD: module type is ");
- switch (spd[SPD_DRAM_TYPE]) {
- case SPD_DRAM_DDR3:
- printk(BIOS_INFO, "DDR3\n");
- break;
- case SPD_DRAM_LPDDR3:
- printk(BIOS_INFO, "LPDDR3\n");
- break;
- default:
- printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
- break;
- }
-
- /* Module Part Number */
- memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
- spd_name[SPD_PART_LEN] = 0;
- printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
-
- printk(BIOS_INFO,
- "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
- banks, ranks, rows, cols, capmb);
- printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
- devw, busw);
-
- if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
- /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
- printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
- capmb / 8 * busw / devw * ranks);
- }
-}
-
-/* Copy SPD data for on-board memory */
-void mainboard_fill_spd_data(struct pei_data *pei_data)
-{
- char *spd_file;
- size_t spd_file_len;
- int spd_index, spd_span;
-
-
- spd_index = pei_data->mem_cfg_id;
- printk(BIOS_INFO, "SPD index %d\n", spd_index);
-
- /* Load SPD data from CBFS */
- spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
- &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
-
- /* make sure we have at least one SPD in the file. */
- if (spd_file_len < SPD_LEN)
- die("Missing SPD data.");
-
- /* Make sure we did not overrun the buffer */
- if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
- printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
- spd_index = 0;
- }
-
- /* Assume same memory in both channels */
- spd_span = spd_index * SPD_LEN;
- memcpy(pei_data->spd_data[0][0], spd_file + spd_span, SPD_LEN);
-
- if (spd_index != MEM_SINGLE_CHAN0 && spd_index != MEM_SINGLE_CHAN3
- && spd_index != MEM_SINGLE_CHAN4 && spd_index != MEM_SINGLE_CHAN7
- && spd_index != MEM_SINGLE_CHANB && spd_index != MEM_SINGLE_CHANC) {
- memcpy(pei_data->spd_data[1][0], spd_file + spd_span, SPD_LEN);
- printk(BIOS_INFO, "Dual channel SPD detected writing second channel\n");
- }
-
- /* Make sure a valid SPD was found */
- if (pei_data->spd_data[0][0][0] == 0)
- die("Invalid SPD data.");
-
- mainboard_print_spd_info(pei_data->spd_data[0][0]);
-}
diff --git a/src/mainboard/google/lars/spd/spd.h b/src/mainboard/google/lars/spd/spd.h
deleted file mode 100644
index 25cce5e..0000000
--- a/src/mainboard/google/lars/spd/spd.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_SPD_H
-#define MAINBOARD_SPD_H
-
-#define SPD_LEN 256
-
-#define SPD_DRAM_TYPE 2
-#define SPD_DRAM_DDR3 0x0b
-#define SPD_DRAM_LPDDR3 0xf1
-#define SPD_DENSITY_BANKS 4
-#define SPD_ADDRESSING 5
-#define SPD_ORGANIZATION 7
-#define SPD_BUS_DEV_WIDTH 8
-#define SPD_PART_OFF 128
-#define SPD_PART_LEN 18
-#define SPD_MANU_OFF 148
-
-#define MEM_SINGLE_CHAN0 0x0
-#define MEM_SINGLE_CHAN3 0x3
-#define MEM_SINGLE_CHAN4 0x4
-#define MEM_SINGLE_CHAN7 0x7
-#define MEM_SINGLE_CHANB 0xb
-#define MEM_SINGLE_CHANC 0xc
-#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iab37f1b92b0f3a5d99796f916a6fdcc14ce4eef4
Gerrit-Change-Number: 27413
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
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