<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27413">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/lars: Convert to a variant of glados<br><br>Convert lars to a variant of glados Skylake reference board:<br>- add lars-specific DPTF, EC config, GPIO config, Kconfig,<br> NHLT config, PEI data, VBT, SPD data, and devicetree<br>- add conditional generation of NHLT ACPI data for Maxim codec,<br> including override of OEM ID and OEM table ID<br>- remove existing lars board/directory<br><br>Test: build/boot google/lars, verify functionality unchanged<br>from pre-variant configuration<br><br>Change-Id: Iab37f1b92b0f3a5d99796f916a6fdcc14ce4eef4<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/google/glados/Kconfig<br>M src/mainboard/google/glados/Kconfig.name<br>M src/mainboard/google/glados/mainboard.c<br>R src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex<br>R src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex<br>R src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex<br>R src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex<br>R src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex<br>R src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex<br>R src/mainboard/google/glados/variants/lars/Makefile.inc<br>R src/mainboard/google/glados/variants/lars/data.vbt<br>R src/mainboard/google/glados/variants/lars/devicetree.cb<br>R src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl<br>R src/mainboard/google/glados/variants/lars/include/variant/acpi/mainboard.asl<br>R src/mainboard/google/glados/variants/lars/include/variant/ec.h<br>R src/mainboard/google/glados/variants/lars/include/variant/gpio.h<br>R src/mainboard/google/glados/variants/lars/variant.c<br>D src/mainboard/google/lars/Kconfig<br>D src/mainboard/google/lars/Kconfig.name<br>D src/mainboard/google/lars/Makefile.inc<br>D src/mainboard/google/lars/acpi/ec.asl<br>D src/mainboard/google/lars/acpi/superio.asl<br>D src/mainboard/google/lars/board_info.txt<br>D src/mainboard/google/lars/bootblock_mainboard.c<br>D src/mainboard/google/lars/chromeos.c<br>D src/mainboard/google/lars/chromeos.fmd<br>D src/mainboard/google/lars/cmos.layout<br>D src/mainboard/google/lars/dsdt.asl<br>D src/mainboard/google/lars/ec.c<br>D src/mainboard/google/lars/ec.h<br>D src/mainboard/google/lars/mainboard.c<br>D src/mainboard/google/lars/ramstage.c<br>D src/mainboard/google/lars/romstage.c<br>D src/mainboard/google/lars/smihandler.c<br>D src/mainboard/google/lars/spd/empty.spd.hex<br>D src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866.spd.hex<br>D src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866.spd.hex<br>D src/mainboard/google/lars/spd/spd.c<br>D src/mainboard/google/lars/spd/spd.h<br>39 files changed, 129 insertions(+), 1,124 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/27413/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig</span><br><span>index 9ef8736..99e538f 100644</span><br><span>--- a/src/mainboard/google/glados/Kconfig</span><br><span>+++ b/src/mainboard/google/glados/Kconfig</span><br><span>@@ -38,6 +38,7 @@</span><br><span> string</span><br><span> default "Chell" if BOARD_GOOGLE_CHELL</span><br><span> default "Glados" if BOARD_GOOGLE_GLADOS</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Lars" if BOARD_GOOGLE_LARS</span><br><span> </span><br><span> config MAINBOARD_FAMILY</span><br><span> string</span><br><span>@@ -47,11 +48,13 @@</span><br><span> string</span><br><span> default "chell" if BOARD_GOOGLE_CHELL</span><br><span> default "glados" if BOARD_GOOGLE_GLADOS</span><br><span style="color: hsl(120, 100%, 40%);">+ default "lars" if BOARD_GOOGLE_LARS</span><br><span> </span><br><span> config DEVICETREE</span><br><span> string</span><br><span> default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL</span><br><span> default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/lars/devicetree.cb" if BOARD_GOOGLE_LARS</span><br><span> </span><br><span> config MAX_CPUS</span><br><span> int</span><br><span>@@ -70,15 +73,18 @@</span><br><span> string</span><br><span> default "chell" if BOARD_GOOGLE_CHELL</span><br><span> default "glados" if BOARD_GOOGLE_GLADOS</span><br><span style="color: hsl(120, 100%, 40%);">+ default ""</span><br><span> </span><br><span> config EC_GOOGLE_CHROMEEC_PD_BOARDNAME</span><br><span> string</span><br><span> default "chell_pd" if BOARD_GOOGLE_CHELL</span><br><span> default "glados_pd" if BOARD_GOOGLE_GLADOS</span><br><span style="color: hsl(120, 100%, 40%);">+ default ""</span><br><span> </span><br><span> config GBB_HWID</span><br><span> string</span><br><span> depends on CHROMEOS</span><br><span> default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL</span><br><span> default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS</span><br><span style="color: hsl(120, 100%, 40%);">+ default "LARS TEST 5001" if BOARD_GOOGLE_LARS</span><br><span> endif</span><br><span>diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name</span><br><span>index 686107d..1bbeb3e 100644</span><br><span>--- a/src/mainboard/google/glados/Kconfig.name</span><br><span>+++ b/src/mainboard/google/glados/Kconfig.name</span><br><span>@@ -10,3 +10,10 @@</span><br><span> select BOARD_GOOGLE_BASEBOARD_GLADOS</span><br><span> select NHLT_DMIC_4CH</span><br><span> select NHLT_SSM4567</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_GOOGLE_LARS</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "-> Lars (Acer Chromebook 14 for Work (CP5-471))"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_GOOGLE_BASEBOARD_GLADOS</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_GENERIC_MAX98357A</span><br><span style="color: hsl(120, 100%, 40%);">+ select EXCLUDE_NATIVE_SD_INTERFACE</span><br><span style="color: hsl(120, 100%, 40%);">+ select NHLT_MAX98357</span><br><span>diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c</span><br><span>index 921595e..451b3d4 100644</span><br><span>--- a/src/mainboard/google/glados/mainboard.c</span><br><span>+++ b/src/mainboard/google/glados/mainboard.c</span><br><span>@@ -24,6 +24,9 @@</span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span> #include "ec.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static const char *oem_id_maxim = "INTEL";</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *oem_table_id_maxim = "SCRDMAX";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void mainboard_init(struct device *dev)</span><br><span> {</span><br><span> mainboard_ec_init();</span><br><span>@@ -35,6 +38,8 @@</span><br><span> uintptr_t start_addr;</span><br><span> uintptr_t end_addr;</span><br><span> struct nhlt *nhlt;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *oem_id = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *oem_table_id = NULL;</span><br><span> </span><br><span> start_addr = current;</span><br><span> </span><br><span>@@ -57,11 +62,21 @@</span><br><span> if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))</span><br><span> printk(BIOS_ERR, "Couldn't add ssm4567.\n");</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* MAXIM Smart Amps for left and right. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_NHLT_MAX98357)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Couldn't add max98357.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ oem_id = oem_id_maxim;</span><br><span style="color: hsl(120, 100%, 40%);">+ oem_table_id = oem_table_id_maxim;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* NAU88l25 Headset codec. */</span><br><span> if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1))</span><br><span> printk(BIOS_ERR, "Couldn't add headset codec.\n");</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- end_addr = nhlt_soc_serialize(nhlt, start_addr);</span><br><span style="color: hsl(120, 100%, 40%);">+ end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr,</span><br><span style="color: hsl(120, 100%, 40%);">+ oem_id, oem_table_id, 0);</span><br><span> </span><br><span> if (end_addr != start_addr)</span><br><span> acpi_add_table(rsdp, (void *)start_addr);</span><br><span>diff --git a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex</span><br><span>rename to src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex</span><br><span>diff --git a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex</span><br><span>rename to src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex</span><br><span>diff --git a/src/mainboard/google/lars/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex b/src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/google/lars/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex</span><br><span>rename to src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex</span><br><span>diff --git a/src/mainboard/google/lars/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex b/src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/google/lars/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex</span><br><span>rename to src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex</span><br><span>diff --git a/src/mainboard/google/lars/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/google/lars/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex</span><br><span>rename to src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex</span><br><span>diff --git a/src/mainboard/google/lars/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/google/lars/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex</span><br><span>rename to src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex</span><br><span>diff --git a/src/mainboard/google/lars/spd/Makefile.inc b/src/mainboard/google/glados/variants/lars/Makefile.inc</span><br><span>similarity index 89%</span><br><span>rename from src/mainboard/google/lars/spd/Makefile.inc</span><br><span>rename to src/mainboard/google/glados/variants/lars/Makefile.inc</span><br><span>index fff5856..89360a7 100644</span><br><span>--- a/src/mainboard/google/lars/spd/Makefile.inc</span><br><span>+++ b/src/mainboard/google/glados/variants/lars/Makefile.inc</span><br><span>@@ -14,7 +14,8 @@</span><br><span> ## GNU General Public License for more details.</span><br><span> ##</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += spd.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += variant.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += variant.c</span><br><span> </span><br><span> SPD_BIN = $(obj)/spd.bin</span><br><span> </span><br><span>@@ -25,17 +26,16 @@</span><br><span> SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0100 Single Channel 4GB</span><br><span> SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b0101 Dual Channel 8GB</span><br><span> SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 # 0b0110 Dual Channel 4GB</span><br><span style="color: hsl(0, 100%, 40%);">-SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866 # 0b0111 Single Channel 4GB</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b0111 Single Channel 4GB</span><br><span> SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b1000 Dual Channel 4GB</span><br><span> SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107-2G-1866 # 0b1001 Dual Channel 8GB</span><br><span style="color: hsl(0, 100%, 40%);">-SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866 # 0b1010 Dual Channel 4GB</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR # 0b1010 Dual Channel 4GB</span><br><span> SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107-2G-1866 # 0b1011 Single Channel 4GB</span><br><span> SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b1100 Single Channel 4GB</span><br><span style="color: hsl(0, 100%, 40%);">-SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866 # 0b1101 Dual Channel 8GB</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b1101 Dual Channel 8GB</span><br><span> SPD_SOURCES += empty # 0b1110</span><br><span> SPD_SOURCES += empty # 0b1111</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)</span><br><span> </span><br><span> # Include spd ROM data</span><br><span>@@ -48,4 +48,4 @@</span><br><span> </span><br><span> cbfs-files-y += spd.bin</span><br><span> spd.bin-file := $(SPD_BIN)</span><br><span style="color: hsl(0, 100%, 40%);">-spd.bin-type := spd</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-type := spd</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/google/lars/data.vbt b/src/mainboard/google/glados/variants/lars/data.vbt</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/google/lars/data.vbt</span><br><span>rename to src/mainboard/google/glados/variants/lars/data.vbt</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb</span><br><span>similarity index 75%</span><br><span>rename from src/mainboard/google/lars/devicetree.cb</span><br><span>rename to src/mainboard/google/glados/variants/lars/devicetree.cb</span><br><span>index 6bb460a..2eda59b 100644</span><br><span>--- a/src/mainboard/google/lars/devicetree.cb</span><br><span>+++ b/src/mainboard/google/glados/variants/lars/devicetree.cb</span><br><span>@@ -36,6 +36,11 @@</span><br><span> register "Device4Enable" = "1"</span><br><span> register "HeciEnabled" = "0"</span><br><span> register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIrqConfigSirqEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS3MinAssert" = "2" # 50ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS4MinAssert" = "4" # 4s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpSusMinAssert" = "3" # 4s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpAMinAssert" = "3" # 2s</span><br><span> register "PmTimerDisabled" = "1"</span><br><span> </span><br><span> register "pirqa_routing" = "PCH_IRQ11"</span><br><span>@@ -47,22 +52,6 @@</span><br><span> register "pirqg_routing" = "PCH_IRQ11"</span><br><span> register "pirqh_routing" = "PCH_IRQ11"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch</span><br><span style="color: hsl(0, 100%, 40%);">- # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s</span><br><span style="color: hsl(0, 100%, 40%);">- register "PmConfigSlpS3MinAssert" = "0x02"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s</span><br><span style="color: hsl(0, 100%, 40%);">- register "PmConfigSlpS4MinAssert" = "0x04"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s</span><br><span style="color: hsl(0, 100%, 40%);">- register "PmConfigSlpSusMinAssert" = "0x03"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s</span><br><span style="color: hsl(0, 100%, 40%);">- register "PmConfigSlpAMinAssert" = "0x03"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled</span><br><span style="color: hsl(0, 100%, 40%);">- register "SerialIrqConfigSirqEnable" = "0x01"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> # VR Settings Configuration for 5 Domains</span><br><span> #+----------------+-------+-------+-------------+-------------+-------+</span><br><span> #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |</span><br><span>@@ -78,67 +67,68 @@</span><br><span> #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |</span><br><span> #+----------------+-------+-------+-------------+-------------+-------+</span><br><span> register "domain_vr_config[VR_SYSTEM_AGENT]" = "{</span><br><span style="color: hsl(0, 100%, 40%);">- .vr_config_enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi1threshold = 0x50, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi2threshold = 0x10, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi3threshold = 0x4, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi3enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi4enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .imon_slope = 0x0, \</span><br><span style="color: hsl(0, 100%, 40%);">- .imon_offset = 0x0, \</span><br><span style="color: hsl(0, 100%, 40%);">- .icc_max = 0x1C, \</span><br><span style="color: hsl(0, 100%, 40%);">- .voltage_limit = 0x5F0 \</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(4),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(7),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span> }"</span><br><span> </span><br><span> register "domain_vr_config[VR_IA_CORE]" = "{</span><br><span style="color: hsl(0, 100%, 40%);">- .vr_config_enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi1threshold = 0x50, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi2threshold = 0x14, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi3threshold = 0x4, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi3enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi4enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .imon_slope = 0x0, \</span><br><span style="color: hsl(0, 100%, 40%);">- .imon_offset = 0x0, \</span><br><span style="color: hsl(0, 100%, 40%);">- .icc_max = 0x88, \</span><br><span style="color: hsl(0, 100%, 40%);">- .voltage_limit = 0x5F0 \</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(34),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span> }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> register "domain_vr_config[VR_RING]" = "{</span><br><span style="color: hsl(0, 100%, 40%);">- .vr_config_enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi1threshold = 0x50, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi2threshold = 0x14, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi3threshold = 0x4, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi3enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi4enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .imon_slope = 0x0, \</span><br><span style="color: hsl(0, 100%, 40%);">- .imon_offset = 0x0, \</span><br><span style="color: hsl(0, 100%, 40%);">- .icc_max = 0x88, \</span><br><span style="color: hsl(0, 100%, 40%);">- .voltage_limit = 0x5F0, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(34),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span> }"</span><br><span> </span><br><span> register "domain_vr_config[VR_GT_UNSLICED]" = "{</span><br><span style="color: hsl(0, 100%, 40%);">- .vr_config_enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi1threshold = 0x50, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi2threshold = 0x14, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi3threshold = 0x4, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi3enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi4enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .imon_slope = 0x0, \</span><br><span style="color: hsl(0, 100%, 40%);">- .imon_offset = 0x0, \</span><br><span style="color: hsl(0, 100%, 40%);">- .icc_max = 0x8C ,\</span><br><span style="color: hsl(0, 100%, 40%);">- .voltage_limit = 0x5F0 \</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(35),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span> }"</span><br><span> </span><br><span> register "domain_vr_config[VR_GT_SLICED]" = "{</span><br><span style="color: hsl(0, 100%, 40%);">- .vr_config_enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi1threshold = 0x50, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi2threshold = 0x14, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi3threshold = 0x4, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi3enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .psi4enable = 1, \</span><br><span style="color: hsl(0, 100%, 40%);">- .imon_slope = 0x0, \</span><br><span style="color: hsl(0, 100%, 40%);">- .imon_offset = 0x0, \</span><br><span style="color: hsl(0, 100%, 40%);">- .icc_max = 0x8C, \</span><br><span style="color: hsl(0, 100%, 40%);">- .voltage_limit = 0x5F0 \</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(35),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span> }"</span><br><span> </span><br><span> # Enable Root port 1.</span><br><span>@@ -163,18 +153,18 @@</span><br><span> register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V</span><br><span> </span><br><span> # Must leave UART0 enabled or SD/eMMC will not work as PCI</span><br><span style="color: hsl(0, 100%, 40%);">- register "SerialIoDevMode" = "{ \</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexI2C0] = PchSerialIoPci, \</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexI2C1] = PchSerialIoPci, \</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexI2C4] = PchSerialIoPci, \</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexUart0] = PchSerialIoPci, \</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexUart1] = PchSerialIoDisabled, \</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoDevMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C1] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C4] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,</span><br><span> }"</span><br><span> </span><br><span> # PL2 override 25W</span><br><span>diff --git a/src/mainboard/google/lars/acpi/dptf.asl b/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl</span><br><span>similarity index 97%</span><br><span>rename from src/mainboard/google/lars/acpi/dptf.asl</span><br><span>rename to src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl</span><br><span>index c85e1b6..1f464c5 100644</span><br><span>--- a/src/mainboard/google/lars/acpi/dptf.asl</span><br><span>+++ b/src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl</span><br><span>@@ -132,6 +132,3 @@</span><br><span> 1000 /* StepSize */</span><br><span> }</span><br><span> })</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Include DPTF */</span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/intel/skylake/acpi/dptf/dptf.asl></span><br><span>diff --git a/src/mainboard/google/lars/acpi_tables.c b/src/mainboard/google/glados/variants/lars/include/variant/acpi/mainboard.asl</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/google/lars/acpi_tables.c</span><br><span>rename to src/mainboard/google/glados/variants/lars/include/variant/acpi/mainboard.asl</span><br><span>diff --git a/src/mainboard/google/lars/acpi/mainboard.asl b/src/mainboard/google/glados/variants/lars/include/variant/ec.h</span><br><span>similarity index 72%</span><br><span>rename from src/mainboard/google/lars/acpi/mainboard.asl</span><br><span>rename to src/mainboard/google/glados/variants/lars/include/variant/ec.h</span><br><span>index 861d39f..3c094b5 100644</span><br><span>--- a/src/mainboard/google/lars/acpi/mainboard.asl</span><br><span>+++ b/src/mainboard/google/glados/variants/lars/include/variant/ec.h</span><br><span>@@ -1,8 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Google Inc.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -14,12 +13,8 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include "../gpio.h"</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable EC backed ALS device in ACPI */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_ALS_DEVICE</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-Scope (\_SB)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- Device (PWRB)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_HID, EisaId ("PNP0C0C"))</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable EC backed Keyboard Backlight in ACPI */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_KEYBOARD_BACKLIGHT</span><br><span>diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/google/lars/gpio.h</span><br><span>rename to src/mainboard/google/glados/variants/lars/include/variant/gpio.h</span><br><span>diff --git a/src/mainboard/google/lars/pei_data.c b/src/mainboard/google/glados/variants/lars/variant.c</span><br><span>similarity index 72%</span><br><span>rename from src/mainboard/google/lars/pei_data.c</span><br><span>rename to src/mainboard/google/glados/variants/lars/variant.c</span><br><span>index 67d8644..297b149 100644</span><br><span>--- a/src/mainboard/google/lars/pei_data.c</span><br><span>+++ b/src/mainboard/google/glados/variants/lars/variant.c</span><br><span>@@ -16,14 +16,18 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variant.h></span><br><span> #include <soc/pei_data.h></span><br><span> #include <soc/pei_wrapper.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "boardid.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* PCH_MEM_CFG[3:0] */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAX_MEMORY_CONFIG 0x10</span><br><span> #define K4E6E304EB_MEM_ID 0x5</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCOMP_TARGET_PARAMS 0x5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MEM_SINGLE_CHAN0 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define MEM_SINGLE_CHAN3 0x3</span><br><span style="color: hsl(120, 100%, 40%);">+#define MEM_SINGLE_CHAN4 0x4</span><br><span style="color: hsl(120, 100%, 40%);">+#define MEM_SINGLE_CHAN7 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#define MEM_SINGLE_CHANB 0xb</span><br><span style="color: hsl(120, 100%, 40%);">+#define MEM_SINGLE_CHANC 0xc</span><br><span> </span><br><span> void mainboard_fill_pei_data(struct pei_data *pei_data)</span><br><span> {</span><br><span>@@ -42,14 +46,10 @@</span><br><span> const u16 RcompResistor[3] = { 200, 81, 162 };</span><br><span> </span><br><span> /* Rcomp target */</span><br><span style="color: hsl(0, 100%, 40%);">- static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 100, 40, 40, 23, 40</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(120, 100%, 40%);">+ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };</span><br><span> </span><br><span> /*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EB -EGCF*/</span><br><span style="color: hsl(0, 100%, 40%);">- static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 100, 40, 40, 21, 40</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(120, 100%, 40%);">+ const u16 StrengthendRcompTarget[5] = { 100, 40, 40, 21, 40 };</span><br><span> </span><br><span> /* Default Rcomp Target assignment */</span><br><span> const u16 *targeted_rcomp = RcompTarget;</span><br><span>@@ -57,13 +57,22 @@</span><br><span> memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));</span><br><span> memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));</span><br><span> memcpy(pei_data->RcompResistor, RcompResistor,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(RcompResistor));</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(RcompResistor));</span><br><span> </span><br><span> /* Override Rcomp Target assignment for specific SKU(s) */</span><br><span> if (pei_data->mem_cfg_id == K4E6E304EB_MEM_ID)</span><br><span> targeted_rcomp = StrengthendRcompTarget;</span><br><span> </span><br><span> memcpy(pei_data->RcompTarget, targeted_rcomp,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(pei_data->RcompTarget));</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(pei_data->RcompTarget));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+int is_dual_channel(const int spd_index)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return (spd_index != MEM_SINGLE_CHAN0</span><br><span style="color: hsl(120, 100%, 40%);">+ && spd_index != MEM_SINGLE_CHAN3</span><br><span style="color: hsl(120, 100%, 40%);">+ && spd_index != MEM_SINGLE_CHAN4</span><br><span style="color: hsl(120, 100%, 40%);">+ && spd_index != MEM_SINGLE_CHAN7</span><br><span style="color: hsl(120, 100%, 40%);">+ && spd_index != MEM_SINGLE_CHANB</span><br><span style="color: hsl(120, 100%, 40%);">+ && spd_index != MEM_SINGLE_CHANC);</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig</span><br><span>deleted file mode 100644</span><br><span>index 9f74fec..0000000</span><br><span>--- a/src/mainboard/google/lars/Kconfig</span><br><span>+++ /dev/null</span><br><span>@@ -1,65 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_GOOGLE_LARS</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span style="color: hsl(0, 100%, 40%);">- def_bool y</span><br><span style="color: hsl(0, 100%, 40%);">- select BOARD_ROMSIZE_KB_16384</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_GENERIC_MAX98357A</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_I2C_GENERIC</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_I2C_NAU8825</span><br><span style="color: hsl(0, 100%, 40%);">- select EC_GOOGLE_CHROMEEC</span><br><span style="color: hsl(0, 100%, 40%);">- select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP</span><br><span style="color: hsl(0, 100%, 40%);">- select EC_GOOGLE_CHROMEEC_BOARDID</span><br><span style="color: hsl(0, 100%, 40%);">- select EC_GOOGLE_CHROMEEC_LPC</span><br><span style="color: hsl(0, 100%, 40%);">- select EC_GOOGLE_CHROMEEC_MEC</span><br><span style="color: hsl(0, 100%, 40%);">- select EC_GOOGLE_CHROMEEC_PD</span><br><span style="color: hsl(0, 100%, 40%);">- select EXCLUDE_NATIVE_SD_INTERFACE</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_ACPI_RESUME</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_ACPI_TABLES</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_OPTION_TABLE</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_SMI_HANDLER</span><br><span style="color: hsl(0, 100%, 40%);">- select INTEL_GMA_HAVE_VBT</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_CHROMEOS</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_LPC_TPM</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_TPM1</span><br><span style="color: hsl(0, 100%, 40%);">- select SOC_INTEL_SKYLAKE</span><br><span style="color: hsl(0, 100%, 40%);">- select SYSTEM_TYPE_LAPTOP</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config VBOOT</span><br><span style="color: hsl(0, 100%, 40%);">- select EC_GOOGLE_CHROMEEC_SWITCHES</span><br><span style="color: hsl(0, 100%, 40%);">- select VBOOT_LID_SWITCH</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config IRQ_SLOT_COUNT</span><br><span style="color: hsl(0, 100%, 40%);">- int</span><br><span style="color: hsl(0, 100%, 40%);">- default 18</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_DIR</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "google/lars"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "Lars"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_FAMILY</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "Google_Lars"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAX_CPUS</span><br><span style="color: hsl(0, 100%, 40%);">- int</span><br><span style="color: hsl(0, 100%, 40%);">- default 8</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config TPM_PIRQ</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x18 # GPP_E0_IRQ</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config INCLUDE_NHLT_BLOBS</span><br><span style="color: hsl(0, 100%, 40%);">- bool "Include blobs for audio."</span><br><span style="color: hsl(0, 100%, 40%);">- select NHLT_DMIC_2CH</span><br><span style="color: hsl(0, 100%, 40%);">- select NHLT_MAX98357</span><br><span style="color: hsl(0, 100%, 40%);">- select NHLT_NAU88L25</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config GBB_HWID</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- depends on CHROMEOS</span><br><span style="color: hsl(0, 100%, 40%);">- default "LARS TEST 5001"</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span>diff --git a/src/mainboard/google/lars/Kconfig.name b/src/mainboard/google/lars/Kconfig.name</span><br><span>deleted file mode 100644</span><br><span>index 8ab4923..0000000</span><br><span>--- a/src/mainboard/google/lars/Kconfig.name</span><br><span>+++ /dev/null</span><br><span>@@ -1,2 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_GOOGLE_LARS</span><br><span style="color: hsl(0, 100%, 40%);">- bool "Lars (Acer Chromebook 14 for Work (CP5-471))"</span><br><span>diff --git a/src/mainboard/google/lars/Makefile.inc b/src/mainboard/google/lars/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index c8480f3..0000000</span><br><span>--- a/src/mainboard/google/lars/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,34 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">-## Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">-## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-## GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += spd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += bootblock_mainboard.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += pei_data.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(0, 100%, 40%);">-verstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += mainboard.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += pei_data.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += ramstage.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span>diff --git a/src/mainboard/google/lars/acpi/ec.asl b/src/mainboard/google/lars/acpi/ec.asl</span><br><span>deleted file mode 100644</span><br><span>index d90d87d..0000000</span><br><span>--- a/src/mainboard/google/lars/acpi/ec.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,34 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* mainboard configuration */</span><br><span style="color: hsl(0, 100%, 40%);">-#include "../ec.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "../gpio.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Enable EC backed ALS device in ACPI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_ENABLE_ALS_DEVICE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Enable EC backed Keyboard Backlight in ACPI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_ENABLE_KEYBOARD_BACKLIGHT</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Enable EC backed PD MCU device in ACPI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_ENABLE_PD_MCU_DEVICE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Enable LID switch and provide wake pin for EC */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_ENABLE_LID_SWITCH</span><br><span style="color: hsl(0, 100%, 40%);">-#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* ACPI code for EC functions */</span><br><span style="color: hsl(0, 100%, 40%);">-#include <ec/google/chromeec/acpi/ec.asl></span><br><span>diff --git a/src/mainboard/google/lars/acpi/superio.asl b/src/mainboard/google/lars/acpi/superio.asl</span><br><span>deleted file mode 100644</span><br><span>index 803d2e3..0000000</span><br><span>--- a/src/mainboard/google/lars/acpi/superio.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,24 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* mainboard configuration */</span><br><span style="color: hsl(0, 100%, 40%);">-#include "../ec.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources</span><br><span style="color: hsl(0, 100%, 40%);">-#define SIO_EC_HOST_ENABLE // EC Host Interface Resources</span><br><span style="color: hsl(0, 100%, 40%);">-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* ACPI code for EC SuperIO functions */</span><br><span style="color: hsl(0, 100%, 40%);">-#include <ec/google/chromeec/acpi/superio.asl></span><br><span>diff --git a/src/mainboard/google/lars/board_info.txt b/src/mainboard/google/lars/board_info.txt</span><br><span>deleted file mode 100644</span><br><span>index 8547dda..0000000</span><br><span>--- a/src/mainboard/google/lars/board_info.txt</span><br><span>+++ /dev/null</span><br><span>@@ -1,6 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-Vendor name: Google</span><br><span style="color: hsl(0, 100%, 40%);">-Board name: Lars Skylake chromebook</span><br><span style="color: hsl(0, 100%, 40%);">-Category: laptop</span><br><span style="color: hsl(0, 100%, 40%);">-ROM protocol: SPI</span><br><span style="color: hsl(0, 100%, 40%);">-ROM socketed: n</span><br><span style="color: hsl(0, 100%, 40%);">-Flashrom support: y</span><br><span>diff --git a/src/mainboard/google/lars/bootblock_mainboard.c b/src/mainboard/google/lars/bootblock_mainboard.c</span><br><span>deleted file mode 100644</span><br><span>index 627b4e8..0000000</span><br><span>--- a/src/mainboard/google/lars/bootblock_mainboard.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,31 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2016 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <bootblock_common.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "gpio.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void early_config_gpio(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* This is a hack for FSP because it does things in MemoryInit()</span><br><span style="color: hsl(0, 100%, 40%);">- * which it shouldn't do. We have to prepare certain gpios here</span><br><span style="color: hsl(0, 100%, 40%);">- * because of the brokenness in FSP. */</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_mainboard_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- early_config_gpio();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/lars/chromeos.c b/src/mainboard/google/lars/chromeos.c</span><br><span>deleted file mode 100644</span><br><span>index 54f9bbe..0000000</span><br><span>--- a/src/mainboard/google/lars/chromeos.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,57 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <rules.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include "gpio.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if ENV_RAMSTAGE</span><br><span style="color: hsl(0, 100%, 40%);">-#include <boot/coreboot_tables.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void fill_lb_gpios(struct lb_gpios *gpios)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct lb_gpio chromeos_gpios[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},</span><br><span style="color: hsl(0, 100%, 40%);">- {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},</span><br><span style="color: hsl(0, 100%, 40%);">- {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},</span><br><span style="color: hsl(0, 100%, 40%);">- {-1, ACTIVE_HIGH, 0, "power"},</span><br><span style="color: hsl(0, 100%, 40%);">- {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},</span><br><span style="color: hsl(0, 100%, 40%);">- {GPIO_EC_IN_RW, ACTIVE_HIGH,</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_get(GPIO_EC_IN_RW), "EC in RW"},</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* ENV_RAMSTAGE */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int get_write_protect_state(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Read PCH_WP GPIO. */</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_get(GPIO_PCH_WP);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct cros_gpio cros_gpios[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(0, 100%, 40%);">- CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_chromeos_acpi_generate(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/lars/chromeos.fmd b/src/mainboard/google/lars/chromeos.fmd</span><br><span>deleted file mode 100644</span><br><span>index 58b6127..0000000</span><br><span>--- a/src/mainboard/google/lars/chromeos.fmd</span><br><span>+++ /dev/null</span><br><span>@@ -1,38 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-FLASH@0xff000000 0x1000000 {</span><br><span style="color: hsl(0, 100%, 40%);">- SI_ALL@0x0 0x200000 {</span><br><span style="color: hsl(0, 100%, 40%);">- SI_DESC@0x0 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">- SI_ME@0x1000 0x1ff000</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- SI_BIOS@0x200000 0xe00000 {</span><br><span style="color: hsl(0, 100%, 40%);">- RW_SECTION_A@0x0 0x3f0000 {</span><br><span style="color: hsl(0, 100%, 40%);">- VBLOCK_A@0x0 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">- FW_MAIN_A(CBFS)@0x10000 0x3dffc0</span><br><span style="color: hsl(0, 100%, 40%);">- RW_FWID_A@0x3effc0 0x40</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_SECTION_B@0x3f0000 0x3f0000 {</span><br><span style="color: hsl(0, 100%, 40%);">- VBLOCK_B@0x0 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">- FW_MAIN_B(CBFS)@0x10000 0x3dffc0</span><br><span style="color: hsl(0, 100%, 40%);">- RW_FWID_B@0x3effc0 0x40</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_MRC_CACHE@0x7e0000 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_ELOG@0x7f0000 0x4000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_SHARED@0x7f4000 0x4000 {</span><br><span style="color: hsl(0, 100%, 40%);">- SHARED_DATA@0x0 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">- VBLOCK_DEV@0x2000 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_VPD@0x7f8000 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_NVRAM@0x7fa000 0x6000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_LEGACY(CBFS)@0x800000 0x200000</span><br><span style="color: hsl(0, 100%, 40%);">- WP_RO@0xa00000 0x400000 {</span><br><span style="color: hsl(0, 100%, 40%);">- RO_VPD@0x0 0x4000</span><br><span style="color: hsl(0, 100%, 40%);">- RO_UNUSED@0x4000 0xc000</span><br><span style="color: hsl(0, 100%, 40%);">- RO_SECTION@0x10000 0x3f0000 {</span><br><span style="color: hsl(0, 100%, 40%);">- FMAP@0x0 0x800</span><br><span style="color: hsl(0, 100%, 40%);">- RO_FRID@0x800 0x40</span><br><span style="color: hsl(0, 100%, 40%);">- RO_FRID_PAD@0x840 0x7c0</span><br><span style="color: hsl(0, 100%, 40%);">- GBB@0x1000 0xef000</span><br><span style="color: hsl(0, 100%, 40%);">- COREBOOT(CBFS)@0xf0000 0x300000</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/lars/cmos.layout b/src/mainboard/google/lars/cmos.layout</span><br><span>deleted file mode 100644</span><br><span>index d032d60..0000000</span><br><span>--- a/src/mainboard/google/lars/cmos.layout</span><br><span>+++ /dev/null</span><br><span>@@ -1,125 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">-## Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">-## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-## GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# -----------------------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-entries</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#start-bit length config config-ID name</span><br><span style="color: hsl(0, 100%, 40%);">-#0 8 r 0 seconds</span><br><span style="color: hsl(0, 100%, 40%);">-#8 8 r 0 alarm_seconds</span><br><span style="color: hsl(0, 100%, 40%);">-#16 8 r 0 minutes</span><br><span style="color: hsl(0, 100%, 40%);">-#24 8 r 0 alarm_minutes</span><br><span style="color: hsl(0, 100%, 40%);">-#32 8 r 0 hours</span><br><span style="color: hsl(0, 100%, 40%);">-#40 8 r 0 alarm_hours</span><br><span style="color: hsl(0, 100%, 40%);">-#48 8 r 0 day_of_week</span><br><span style="color: hsl(0, 100%, 40%);">-#56 8 r 0 day_of_month</span><br><span style="color: hsl(0, 100%, 40%);">-#64 8 r 0 month</span><br><span style="color: hsl(0, 100%, 40%);">-#72 8 r 0 year</span><br><span style="color: hsl(0, 100%, 40%);">-# -----------------------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-# Status Register A</span><br><span style="color: hsl(0, 100%, 40%);">-#80 4 r 0 rate_select</span><br><span style="color: hsl(0, 100%, 40%);">-#84 3 r 0 REF_Clock</span><br><span style="color: hsl(0, 100%, 40%);">-#87 1 r 0 UIP</span><br><span style="color: hsl(0, 100%, 40%);">-# -----------------------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-# Status Register B</span><br><span style="color: hsl(0, 100%, 40%);">-#88 1 r 0 auto_switch_DST</span><br><span style="color: hsl(0, 100%, 40%);">-#89 1 r 0 24_hour_mode</span><br><span style="color: hsl(0, 100%, 40%);">-#90 1 r 0 binary_values_enable</span><br><span style="color: hsl(0, 100%, 40%);">-#91 1 r 0 square-wave_out_enable</span><br><span style="color: hsl(0, 100%, 40%);">-#92 1 r 0 update_finished_enable</span><br><span style="color: hsl(0, 100%, 40%);">-#93 1 r 0 alarm_interrupt_enable</span><br><span style="color: hsl(0, 100%, 40%);">-#94 1 r 0 periodic_interrupt_enable</span><br><span style="color: hsl(0, 100%, 40%);">-#95 1 r 0 disable_clock_updates</span><br><span style="color: hsl(0, 100%, 40%);">-# -----------------------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-# Status Register C</span><br><span style="color: hsl(0, 100%, 40%);">-#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(0, 100%, 40%);">-#100 1 r 0 uf_flag</span><br><span style="color: hsl(0, 100%, 40%);">-#101 1 r 0 af_flag</span><br><span style="color: hsl(0, 100%, 40%);">-#102 1 r 0 pf_flag</span><br><span style="color: hsl(0, 100%, 40%);">-#103 1 r 0 irqf_flag</span><br><span style="color: hsl(0, 100%, 40%);">-# -----------------------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-# Status Register D</span><br><span style="color: hsl(0, 100%, 40%);">-#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(0, 100%, 40%);">-#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(0, 100%, 40%);">-# -----------------------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-# Diagnostic Status Register</span><br><span style="color: hsl(0, 100%, 40%);">-#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# -----------------------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-0 120 r 0 reserved_memory</span><br><span style="color: hsl(0, 100%, 40%);">-#120 264 r 0 unused</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# -----------------------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(0, 100%, 40%);">-384 1 e 4 boot_option</span><br><span style="color: hsl(0, 100%, 40%);">-388 4 h 0 reboot_counter</span><br><span style="color: hsl(0, 100%, 40%);">-#390 2 r 0 unused?</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# -----------------------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-# coreboot config options: console</span><br><span style="color: hsl(0, 100%, 40%);">-#392 3 r 0 unused</span><br><span style="color: hsl(0, 100%, 40%);">-395 4 e 6 debug_level</span><br><span style="color: hsl(0, 100%, 40%);">-#399 1 r 0 unused</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# coreboot config options: cpu</span><br><span style="color: hsl(0, 100%, 40%);">-400 1 e 2 hyper_threading</span><br><span style="color: hsl(0, 100%, 40%);">-#401 7 r 0 unused</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# coreboot config options: southbridge</span><br><span style="color: hsl(0, 100%, 40%);">-408 1 e 1 nmi</span><br><span style="color: hsl(0, 100%, 40%);">-409 2 e 7 power_on_after_fail</span><br><span style="color: hsl(0, 100%, 40%);">-#411 5 r 0 unused</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# coreboot config options: bootloader</span><br><span style="color: hsl(0, 100%, 40%);">-#Used by ChromeOS:</span><br><span style="color: hsl(0, 100%, 40%);">-416 128 r 0 vbnv</span><br><span style="color: hsl(0, 100%, 40%);">-#544 440 r 0 unused</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# SandyBridge MRC Scrambler Seed values</span><br><span style="color: hsl(0, 100%, 40%);">-896 32 r 0 mrc_scrambler_seed</span><br><span style="color: hsl(0, 100%, 40%);">-928 32 r 0 mrc_scrambler_seed_s3</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# coreboot config options: check sums</span><br><span style="color: hsl(0, 100%, 40%);">-984 16 h 0 check_sum</span><br><span style="color: hsl(0, 100%, 40%);">-#1000 24 r 0 amd_reserved</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# -----------------------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-enumerations</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ID value text</span><br><span style="color: hsl(0, 100%, 40%);">-1 0 Disable</span><br><span style="color: hsl(0, 100%, 40%);">-1 1 Enable</span><br><span style="color: hsl(0, 100%, 40%);">-2 0 Enable</span><br><span style="color: hsl(0, 100%, 40%);">-2 1 Disable</span><br><span style="color: hsl(0, 100%, 40%);">-4 0 Fallback</span><br><span style="color: hsl(0, 100%, 40%);">-4 1 Normal</span><br><span style="color: hsl(0, 100%, 40%);">-6 0 Emergency</span><br><span style="color: hsl(0, 100%, 40%);">-6 1 Alert</span><br><span style="color: hsl(0, 100%, 40%);">-6 2 Critical</span><br><span style="color: hsl(0, 100%, 40%);">-6 3 Error</span><br><span style="color: hsl(0, 100%, 40%);">-6 4 Warning</span><br><span style="color: hsl(0, 100%, 40%);">-6 5 Notice</span><br><span style="color: hsl(0, 100%, 40%);">-6 6 Info</span><br><span style="color: hsl(0, 100%, 40%);">-6 7 Debug</span><br><span style="color: hsl(0, 100%, 40%);">-6 8 Spew</span><br><span style="color: hsl(0, 100%, 40%);">-7 0 Disable</span><br><span style="color: hsl(0, 100%, 40%);">-7 1 Enable</span><br><span style="color: hsl(0, 100%, 40%);">-7 2 Keep</span><br><span style="color: hsl(0, 100%, 40%);">-# -----------------------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-checksums</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-checksum 392 415 984</span><br><span>diff --git a/src/mainboard/google/lars/dsdt.asl b/src/mainboard/google/lars/dsdt.asl</span><br><span>deleted file mode 100644</span><br><span>index b5a37c6..0000000</span><br><span>--- a/src/mainboard/google/lars/dsdt.asl</span><br><span>+++ /dev/null</span><br><span>@@ -1,55 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-DefinitionBlock(</span><br><span style="color: hsl(0, 100%, 40%);">- "dsdt.aml",</span><br><span style="color: hsl(0, 100%, 40%);">- "DSDT",</span><br><span style="color: hsl(0, 100%, 40%);">- 0x05, // DSDT revision: ACPI v5.0</span><br><span style="color: hsl(0, 100%, 40%);">- "COREv4", // OEM id</span><br><span style="color: hsl(0, 100%, 40%);">- "COREBOOT", // OEM table id</span><br><span style="color: hsl(0, 100%, 40%);">- 0x20110725 // OEM revision</span><br><span style="color: hsl(0, 100%, 40%);">-)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- // Some generic macros</span><br><span style="color: hsl(0, 100%, 40%);">- #include <soc/intel/skylake/acpi/platform.asl></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // global NVS and variables</span><br><span style="color: hsl(0, 100%, 40%);">- #include <soc/intel/skylake/acpi/globalnvs.asl></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // CPU</span><br><span style="color: hsl(0, 100%, 40%);">- #include <soc/intel/skylake/acpi/cpu.asl></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Scope (\_SB) {</span><br><span style="color: hsl(0, 100%, 40%);">- Device (PCI0)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- #include <soc/intel/skylake/acpi/systemagent.asl></span><br><span style="color: hsl(0, 100%, 40%);">- #include <soc/intel/skylake/acpi/pch.asl></span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Dynamic Platform Thermal Framework</span><br><span style="color: hsl(0, 100%, 40%);">- #include "acpi/dptf.asl"</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Chrome OS specific</span><br><span style="color: hsl(0, 100%, 40%);">- #include <vendorcode/google/chromeos/acpi/chromeos.asl></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Chipset specific sleep states</span><br><span style="color: hsl(0, 100%, 40%);">- #include <soc/intel/skylake/acpi/sleepstates.asl></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Mainboard specific</span><br><span style="color: hsl(0, 100%, 40%);">- #include "acpi/mainboard.asl"</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/lars/ec.c b/src/mainboard/google/lars/ec.c</span><br><span>deleted file mode 100644</span><br><span>index 3722378..0000000</span><br><span>--- a/src/mainboard/google/lars/ec.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,34 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <ec/google/chromeec/ec.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "ec.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_ec_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const struct google_chromeec_event_info info = {</span><br><span style="color: hsl(0, 100%, 40%);">- .log_events = MAINBOARD_EC_LOG_EVENTS,</span><br><span style="color: hsl(0, 100%, 40%);">- .sci_events = MAINBOARD_EC_SCI_EVENTS,</span><br><span style="color: hsl(0, 100%, 40%);">- .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,</span><br><span style="color: hsl(0, 100%, 40%);">- .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "mainboard: EC init\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- google_chromeec_events_init(&info, acpi_is_wakeup_s3());</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/lars/ec.h b/src/mainboard/google/lars/ec.h</span><br><span>deleted file mode 100644</span><br><span>index fcb0a70..0000000</span><br><span>--- a/src/mainboard/google/lars/ec.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,58 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef MAINBOARD_EC_H</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_EC_H</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <ec/ec.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <ec/google/chromeec/ec_commands.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_EC_SCI_EVENTS \</span><br><span style="color: hsl(0, 100%, 40%);">- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_EC_SMI_EVENTS \</span><br><span style="color: hsl(0, 100%, 40%);">- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* EC can wake from S5 with lid or power button */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_EC_S5_WAKE_EVENTS \</span><br><span style="color: hsl(0, 100%, 40%);">- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* EC can wake from S3 with lid or power button or key press */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_EC_S3_WAKE_EVENTS \</span><br><span style="color: hsl(0, 100%, 40%);">- (MAINBOARD_EC_S5_WAKE_EVENTS |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Log EC wake events plus EC shutdown events */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_EC_LOG_EVENTS \</span><br><span style="color: hsl(0, 100%, 40%);">- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\</span><br><span style="color: hsl(0, 100%, 40%);">- EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span>diff --git a/src/mainboard/google/lars/mainboard.c b/src/mainboard/google/lars/mainboard.c</span><br><span>deleted file mode 100644</span><br><span>index 43895fb..0000000</span><br><span>--- a/src/mainboard/google/lars/mainboard.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,78 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/nhlt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "ec.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void mainboard_init(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_ec_init();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static unsigned long mainboard_write_acpi_tables(</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *device, unsigned long current, acpi_rsdp_t *rsdp)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t start_addr;</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t end_addr;</span><br><span style="color: hsl(0, 100%, 40%);">- struct nhlt *nhlt;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- start_addr = current;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- nhlt = nhlt_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (nhlt == NULL)</span><br><span style="color: hsl(0, 100%, 40%);">- return start_addr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* 2 Channel DMIC array. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (nhlt_soc_add_dmic_array(nhlt, 2))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* MAXIM Smart Amps for left and right. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Couldn't add max98357.\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* NAU88l25 Headset codec. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Couldn't add headset codec.\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- end_addr = nhlt_soc_serialize(nhlt, start_addr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (end_addr != start_addr)</span><br><span style="color: hsl(0, 100%, 40%);">- acpi_add_table(rsdp, (void *)start_addr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return end_addr;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * mainboard_enable is executed as first thing after</span><br><span style="color: hsl(0, 100%, 40%);">- * enumerate_buses().</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- dev->ops->init = mainboard_init;</span><br><span style="color: hsl(0, 100%, 40%);">- dev->ops->write_acpi_tables = mainboard_write_acpi_tables;</span><br><span style="color: hsl(0, 100%, 40%);">- dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- .enable_dev = mainboard_enable,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span>diff --git a/src/mainboard/google/lars/ramstage.c b/src/mainboard/google/lars/ramstage.c</span><br><span>deleted file mode 100644</span><br><span>index 563c715..0000000</span><br><span>--- a/src/mainboard/google/lars/ramstage.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,24 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2014 Intel Corporation</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/ramstage.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "gpio.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Configure pads prior to SiliconInit() in case there's any</span><br><span style="color: hsl(0, 100%, 40%);">- * dependencies during hardware initialization. */</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/lars/romstage.c b/src/mainboard/google/lars/romstage.c</span><br><span>deleted file mode 100644</span><br><span>index b3ef0d8..0000000</span><br><span>--- a/src/mainboard/google/lars/romstage.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,73 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2010 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <ec/google/chromeec/ec.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pei_data.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pei_wrapper.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/romstage.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "gpio.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "spd/spd.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_romstage_entry(struct romstage_params *params)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* PCH_MEM_CFG[3:0] */</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_t spd_gpios[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_MEM_CONFIG_0,</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_MEM_CONFIG_1,</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_MEM_CONFIG_2,</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_MEM_CONFIG_3,</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Turn on keyboard backlight to indicate we are booting */</span><br><span style="color: hsl(0, 100%, 40%);">- if (params->power_state->prev_sleep_state != ACPI_S3)</span><br><span style="color: hsl(0, 100%, 40%);">- google_chromeec_kbbacklight(25);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios,</span><br><span style="color: hsl(0, 100%, 40%);">- ARRAY_SIZE(spd_gpios));</span><br><span style="color: hsl(0, 100%, 40%);">- /* Fill out PEI DATA */</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_fill_pei_data(params->pei_data);</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_fill_spd_data(params->pei_data);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Initialize memory */</span><br><span style="color: hsl(0, 100%, 40%);">- romstage_common(params);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_memory_init_params(struct romstage_params *params,</span><br><span style="color: hsl(0, 100%, 40%);">- MEMORY_INIT_UPD *memory_params)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- if (params->pei_data->spd_data[0][0][0] != 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- memory_params->MemorySpdPtr00 =</span><br><span style="color: hsl(0, 100%, 40%);">- (UINT32)(params->pei_data->spd_data[0][0]);</span><br><span style="color: hsl(0, 100%, 40%);">- memory_params->MemorySpdPtr10 =</span><br><span style="color: hsl(0, 100%, 40%);">- (UINT32)(params->pei_data->spd_data[1][0]);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(params->pei_data->dq_map[0]));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(params->pei_data->dq_map[1]));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(params->pei_data->dqs_map[0]));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(params->pei_data->dqs_map[1]));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(params->pei_data->RcompResistor));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(params->pei_data->RcompTarget));</span><br><span style="color: hsl(0, 100%, 40%);">- memory_params->MemorySpdDataLen = SPD_LEN;</span><br><span style="color: hsl(0, 100%, 40%);">- memory_params->DqPinsInterleaved = FALSE;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/lars/smihandler.c b/src/mainboard/google/lars/smihandler.c</span><br><span>deleted file mode 100644</span><br><span>index 24a5b96..0000000</span><br><span>--- a/src/mainboard/google/lars/smihandler.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,69 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/acpi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <elog.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <ec/google/chromeec/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/iomap.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/nvs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/smm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "ec.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "gpio.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int mainboard_io_trap_handler(int smif)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- switch (smif) {</span><br><span style="color: hsl(0, 100%, 40%);">- case 0x99:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Sample\n");</span><br><span style="color: hsl(0, 100%, 40%);">- smm_get_gnvs()->smif = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- default:</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* On success, the IO Trap Handler returns 0</span><br><span style="color: hsl(0, 100%, 40%);">- * On failure, the IO Trap Handler returns a value != 0</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * For now, we force the return value to 0 and log all traps to</span><br><span style="color: hsl(0, 100%, 40%);">- * see what's going on.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- return 1;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_smi_gpi_handler(const struct gpi_status *sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpi_status_get(sts, EC_SMI_GPI))</span><br><span style="color: hsl(0, 100%, 40%);">- chromeec_smi_process_events();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_smi_sleep(u8 slp_typ)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))</span><br><span style="color: hsl(0, 100%, 40%);">- chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,</span><br><span style="color: hsl(0, 100%, 40%);">- MAINBOARD_EC_S5_WAKE_EVENTS);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int mainboard_smi_apmc(u8 apmc)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))</span><br><span style="color: hsl(0, 100%, 40%);">- chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,</span><br><span style="color: hsl(0, 100%, 40%);">- MAINBOARD_EC_SMI_EVENTS);</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/lars/spd/empty.spd.hex b/src/mainboard/google/lars/spd/empty.spd.hex</span><br><span>deleted file mode 100644</span><br><span>index 9ec39f1..0000000</span><br><span>--- a/src/mainboard/google/lars/spd/empty.spd.hex</span><br><span>+++ /dev/null</span><br><span>@@ -1,16 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866.spd.hex b/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866.spd.hex</span><br><span>deleted file mode 100644</span><br><span>index 5c1332e..0000000</span><br><span>--- a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8GTALAR-NUD-1G-1866.spd.hex</span><br><span>+++ /dev/null</span><br><span>@@ -1,16 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-91 20 F1 03 05 19 05 03 03 11 01 08 09 00 40 05</span><br><span style="color: hsl(0, 100%, 40%);">-78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-48 39 43 43 4E 4E 4E 38 47 54 41 4C 41 52 2D 4E</span><br><span style="color: hsl(0, 100%, 40%);">-55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866.spd.hex b/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866.spd.hex</span><br><span>deleted file mode 100644</span><br><span>index 7c7c8d2..0000000</span><br><span>--- a/src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBJTALAR-NUD-2G-1866.spd.hex</span><br><span>+++ /dev/null</span><br><span>@@ -1,16 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05</span><br><span style="color: hsl(0, 100%, 40%);">-78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-48 39 43 43 4E 4E 4E 42 4A 54 41 4C 41 52 2D 4E</span><br><span style="color: hsl(0, 100%, 40%);">-55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span style="color: hsl(0, 100%, 40%);">-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>diff --git a/src/mainboard/google/lars/spd/spd.c b/src/mainboard/google/lars/spd/spd.c</span><br><span>deleted file mode 100644</span><br><span>index d9fe579..0000000</span><br><span>--- a/src/mainboard/google/lars/spd/spd.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,120 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/byteorder.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cbfs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pei_data.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/romstage.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include "spd.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void mainboard_print_spd_info(uint8_t spd[])</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };</span><br><span style="color: hsl(0, 100%, 40%);">- const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };</span><br><span style="color: hsl(0, 100%, 40%);">- const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };</span><br><span style="color: hsl(0, 100%, 40%);">- const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };</span><br><span style="color: hsl(0, 100%, 40%);">- const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };</span><br><span style="color: hsl(0, 100%, 40%);">- const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };</span><br><span style="color: hsl(0, 100%, 40%);">- const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };</span><br><span style="color: hsl(0, 100%, 40%);">- char spd_name[SPD_PART_LEN+1] = { 0 };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];</span><br><span style="color: hsl(0, 100%, 40%);">- int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;</span><br><span style="color: hsl(0, 100%, 40%);">- int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];</span><br><span style="color: hsl(0, 100%, 40%);">- int cols = spd_cols[spd[SPD_ADDRESSING] & 7];</span><br><span style="color: hsl(0, 100%, 40%);">- int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];</span><br><span style="color: hsl(0, 100%, 40%);">- int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];</span><br><span style="color: hsl(0, 100%, 40%);">- int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Module type */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "SPD: module type is ");</span><br><span style="color: hsl(0, 100%, 40%);">- switch (spd[SPD_DRAM_TYPE]) {</span><br><span style="color: hsl(0, 100%, 40%);">- case SPD_DRAM_DDR3:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "DDR3\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case SPD_DRAM_LPDDR3:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "LPDDR3\n");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- default:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Module Part Number */</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);</span><br><span style="color: hsl(0, 100%, 40%);">- spd_name[SPD_PART_LEN] = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO,</span><br><span style="color: hsl(0, 100%, 40%);">- "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",</span><br><span style="color: hsl(0, 100%, 40%);">- banks, ranks, rows, cols, capmb);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",</span><br><span style="color: hsl(0, 100%, 40%);">- devw, busw);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",</span><br><span style="color: hsl(0, 100%, 40%);">- capmb / 8 * busw / devw * ranks);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Copy SPD data for on-board memory */</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_fill_spd_data(struct pei_data *pei_data)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- char *spd_file;</span><br><span style="color: hsl(0, 100%, 40%);">- size_t spd_file_len;</span><br><span style="color: hsl(0, 100%, 40%);">- int spd_index, spd_span;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- spd_index = pei_data->mem_cfg_id;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "SPD index %d\n", spd_index);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Load SPD data from CBFS */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,</span><br><span style="color: hsl(0, 100%, 40%);">- &spd_file_len);</span><br><span style="color: hsl(0, 100%, 40%);">- if (!spd_file)</span><br><span style="color: hsl(0, 100%, 40%);">- die("SPD data not found.");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* make sure we have at least one SPD in the file. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_file_len < SPD_LEN)</span><br><span style="color: hsl(0, 100%, 40%);">- die("Missing SPD data.");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Make sure we did not overrun the buffer */</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");</span><br><span style="color: hsl(0, 100%, 40%);">- spd_index = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Assume same memory in both channels */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_span = spd_index * SPD_LEN;</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(pei_data->spd_data[0][0], spd_file + spd_span, SPD_LEN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_index != MEM_SINGLE_CHAN0 && spd_index != MEM_SINGLE_CHAN3</span><br><span style="color: hsl(0, 100%, 40%);">- && spd_index != MEM_SINGLE_CHAN4 && spd_index != MEM_SINGLE_CHAN7</span><br><span style="color: hsl(0, 100%, 40%);">- && spd_index != MEM_SINGLE_CHANB && spd_index != MEM_SINGLE_CHANC) {</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(pei_data->spd_data[1][0], spd_file + spd_span, SPD_LEN);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "Dual channel SPD detected writing second channel\n");</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Make sure a valid SPD was found */</span><br><span style="color: hsl(0, 100%, 40%);">- if (pei_data->spd_data[0][0][0] == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- die("Invalid SPD data.");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_print_spd_info(pei_data->spd_data[0][0]);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/lars/spd/spd.h b/src/mainboard/google/lars/spd/spd.h</span><br><span>deleted file mode 100644</span><br><span>index 25cce5e..0000000</span><br><span>--- a/src/mainboard/google/lars/spd/spd.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,39 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef MAINBOARD_SPD_H</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAINBOARD_SPD_H</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPD_LEN 256</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPD_DRAM_TYPE 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPD_DRAM_DDR3 0x0b</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPD_DRAM_LPDDR3 0xf1</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPD_DENSITY_BANKS 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPD_ADDRESSING 5</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPD_ORGANIZATION 7</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPD_BUS_DEV_WIDTH 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPD_PART_OFF 128</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPD_PART_LEN 18</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPD_MANU_OFF 148</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_SINGLE_CHAN0 0x0</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_SINGLE_CHAN3 0x3</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_SINGLE_CHAN4 0x4</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_SINGLE_CHAN7 0x7</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_SINGLE_CHANB 0xb</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_SINGLE_CHANC 0xc</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27413">change 27413</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27413"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iab37f1b92b0f3a5d99796f916a6fdcc14ce4eef4 </div>
<div style="display:none"> Gerrit-Change-Number: 27413 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>