[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Adjust GPD3 pin termination

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30374


Change subject: mb/google/sarien: Adjust GPD3 pin termination
......................................................................

mb/google/sarien: Adjust GPD3 pin termination

Internal pull up need to be enabled for GPD3 as power button pin for
PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will
stay floating and hook up XDP can cause system shutdown as power buttone
event will trigger.

BUG=N/A
TEST=Hook up XDP on sarien platform, able to boot up into OS and stay
at power up state.

Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf
---
M src/mainboard/google/sarien/variants/sarien/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30374/1

diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c
index 38d21c8..3f43e73 100644
--- a/src/mainboard/google/sarien/variants/sarien/gpio.c
+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c
@@ -213,7 +213,6 @@
 /* BATLOW# */		PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */
 /* ACPRESENT */		PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */
 /* LAN_WAKE# */		PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */
-/* PWRBTN# */		PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */
 /* SLP_S3# */		PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */
 /* SLP_S4# */		PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */
 /* SLP_A# */		PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */
@@ -237,6 +236,7 @@
 /* CPU_GP0 */		PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
 /* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
 /* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
+/* PWRBTN# */		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf
Gerrit-Change-Number: 30374
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-MessageType: newchange
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