[coreboot-gerrit] Change in ...coreboot[master]: Revert "mb/google/octopus/variants/fleex: Update Charger throttling s...

Sumeet R Pawnikar (Code Review) gerrit at coreboot.org
Fri Dec 21 17:01:16 CET 2018


Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30366


Change subject: Revert "mb/google/octopus/variants/fleex: Update Charger throttling settings"
......................................................................

Revert "mb/google/octopus/variants/fleex: Update Charger throttling settings"

This reverts commit 969ed357f823659a6861a2ca38f3ad9d7b58f949

Reason for revert:
According to partner issue b:112448519 comment#80, it impacts
skin temperature specifications.

Change-Id: I7603c3816f34adebc1f67eff6fad214557544022
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
---
M src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl
1 file changed, 3 insertions(+), 7 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/30366/1

diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl
index 5f35c33..d5943c7 100644
--- a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl
@@ -26,8 +26,6 @@
 #define DPTF_TSR2_PASSIVE	53
 #define DPTF_TSR2_CRITICAL	127
 
-#define DPTF_ENABLE_CHARGER
-
 /* Charger performance states, board-specific values from charger and EC */
 Name (CHPS, Package () {
 	Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 },	/* 3A (MAX) */
@@ -44,10 +42,8 @@
 	/* CPU Effect on Temp Sensor 1 */
 	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
 
-#ifdef DPTF_ENABLE_CHARGER
-	/* Charger Effect on Temp Sensor 2 */
-	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
-#endif
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
 })
 
 Name (MPPC, Package ()
@@ -55,7 +51,7 @@
 	0x2,		/* Revision */
 	Package () {	/* Power Limit 1 */
 		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
-		3000,	/* PowerLimitMinimum */
+		4500,	/* PowerLimitMinimum */
 		10000,	/* PowerLimitMaximum */
 		1000,	/* TimeWindowMinimum */
 		1000,	/* TimeWindowMaximum */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7603c3816f34adebc1f67eff6fad214557544022
Gerrit-Change-Number: 30366
Gerrit-PatchSet: 1
Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar at intel.com>
Gerrit-MessageType: newchange
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