<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30374">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/sarien: Adjust GPD3 pin termination<br><br>Internal pull up need to be enabled for GPD3 as power button pin for<br>PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will<br>stay floating and hook up XDP can cause system shutdown as power buttone<br>event will trigger.<br><br>BUG=N/A<br>TEST=Hook up XDP on sarien platform, able to boot up into OS and stay<br>at power up state.<br><br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf<br>---<br>M src/mainboard/google/sarien/variants/sarien/gpio.c<br>1 file changed, 1 insertion(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30374/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>index 38d21c8..3f43e73 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c</span><br><span>@@ -213,7 +213,6 @@</span><br><span> /* BATLOW# */            PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */</span><br><span> /* ACPRESENT */             PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */</span><br><span> /* LAN_WAKE# */          PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* PWRBTN# */         PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */</span><br><span> /* SLP_S3# */           PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */</span><br><span> /* SLP_S4# */           PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */</span><br><span> /* SLP_A# */            PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */</span><br><span>@@ -237,6 +236,7 @@</span><br><span> /* CPU_GP0 */              PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */</span><br><span> /* SATALED# */                PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */</span><br><span> /* DDPD_HPD2 */             PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PWRBTN# */              PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */</span><br><span> };</span><br><span> </span><br><span> const struct pad_config *variant_gpio_table(size_t *num)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30374">change 30374</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30374"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf </div>
<div style="display:none"> Gerrit-Change-Number: 30374 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>