[coreboot-gerrit] Change in ...coreboot[master]: src/mainboard/libretrend/lt1000: Initial commit
Michał Żygowski (Code Review)
gerrit at coreboot.org
Fri Dec 21 12:24:08 CET 2018
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30360
Change subject: src/mainboard/libretrend/lt1000: Initial commit
......................................................................
src/mainboard/libretrend/lt1000: Initial commit
Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab
Signed-off-by: Michał Żygowski <michal.zygowski at 3mdeb.com>
---
A src/ec/libretrend/lt1000/Kconfig
A src/ec/libretrend/lt1000/acpi/battery.asl
A src/ec/libretrend/lt1000/acpi/ec.asl
A src/mainboard/libretrend/Kconfig
A src/mainboard/libretrend/Kconfig.name
A src/mainboard/libretrend/lt1000/Kconfig
A src/mainboard/libretrend/lt1000/Kconfig.name
A src/mainboard/libretrend/lt1000/Makefile.inc
A src/mainboard/libretrend/lt1000/acpi/ec.asl
A src/mainboard/libretrend/lt1000/acpi/mainboard.asl
A src/mainboard/libretrend/lt1000/acpi/superio.asl
A src/mainboard/libretrend/lt1000/acpi_tables.c
A src/mainboard/libretrend/lt1000/board_info.txt
A src/mainboard/libretrend/lt1000/boot-menu-wait
A src/mainboard/libretrend/lt1000/bootorder
A src/mainboard/libretrend/lt1000/bootsplash.jpg
A src/mainboard/libretrend/lt1000/devicetree.cb
A src/mainboard/libretrend/lt1000/dsdt.asl
A src/mainboard/libretrend/lt1000/hda_verb.c
A src/mainboard/libretrend/lt1000/hda_verb.h
A src/mainboard/libretrend/lt1000/mainboard.c
A src/mainboard/libretrend/lt1000/mainboard_gpio.h
A src/mainboard/libretrend/lt1000/pei_data.c
A src/mainboard/libretrend/lt1000/pei_data.h
A src/mainboard/libretrend/lt1000/ramstage.c
A src/mainboard/libretrend/lt1000/romstage.c
26 files changed, 1,314 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/30360/1
diff --git a/src/ec/libretrend/lt1000/Kconfig b/src/ec/libretrend/lt1000/Kconfig
new file mode 100644
index 0000000..269dbfc
--- /dev/null
+++ b/src/ec/libretrend/lt1000/Kconfig
@@ -0,0 +1,4 @@
+config EC_LIBRETREND_LT1000
+ bool
+ help
+ Libretrend EC
diff --git a/src/ec/libretrend/lt1000/acpi/battery.asl b/src/ec/libretrend/lt1000/acpi/battery.asl
new file mode 100644
index 0000000..4e3d11d
--- /dev/null
+++ b/src/ec/libretrend/lt1000/acpi/battery.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Libretrend LDA
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (BAT0)
+{
+ Name (_HID, EisaId ("PNP0C0A"))
+ Name (_UID, Zero)
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (Zero)
+ }
+}
+
+Device (BAT1)
+{
+ Name (_HID, EisaId ("PNP0C0A"))
+ Name (_UID, One)
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (Zero)
+ }
+
+ Method (_BST, 0, NotSerialized)
+ {
+ Return (BST1 ())
+ }
+}
+
+Device (BAT2)
+{
+ Name (_HID, EisaId ("PNP0C0A"))
+ Name (_UID, 0x02)
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (Zero)
+ }
+
+ Method (_BST, 0, NotSerialized)
+ {
+ Return (BST2 ())
+ }
+}
diff --git a/src/ec/libretrend/lt1000/acpi/ec.asl b/src/ec/libretrend/lt1000/acpi/ec.asl
new file mode 100644
index 0000000..96367e6
--- /dev/null
+++ b/src/ec/libretrend/lt1000/acpi/ec.asl
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Libretrend LDA
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+Device (EC)
+{
+ Name (_HID, EisaId ("PNP0C09"))
+ Name (_UID, One)
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (Zero)
+ }
+
+ Name (B1ST, 0x32)
+ Name (B2ST, 0x36)
+
+ Method (BST1, 0, NotSerialized)
+ {
+ Name (PKG1, Package (0x04)
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ Return (PKG1)
+ }
+
+ Method (BST2, 0, NotSerialized)
+ {
+ Name (PKG2, Package (0x04)
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ Return (PKG2)
+ }
+
+ #include "battery.asl"
+}
diff --git a/src/mainboard/libretrend/Kconfig b/src/mainboard/libretrend/Kconfig
new file mode 100644
index 0000000..a60995a
--- /dev/null
+++ b/src/mainboard/libretrend/Kconfig
@@ -0,0 +1,31 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Libretrend LDA
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if VENDOR_LIBRETREND
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/libretrend/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/libretrend/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string "Mainboard Vendor"
+ default "Libretrend"
+
+endif # VENDOR_LIBRETREND
diff --git a/src/mainboard/libretrend/Kconfig.name b/src/mainboard/libretrend/Kconfig.name
new file mode 100644
index 0000000..cd272b0
--- /dev/null
+++ b/src/mainboard/libretrend/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_LIBRETREND
+ bool "Libretrend"
diff --git a/src/mainboard/libretrend/lt1000/Kconfig b/src/mainboard/libretrend/lt1000/Kconfig
new file mode 100644
index 0000000..c4e2ccd
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/Kconfig
@@ -0,0 +1,71 @@
+config BOARD_LIBRETREND_BASEBOARD_LT1000
+ def_bool n
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select SOC_INTEL_SKYLAKE
+ select SERIRQ_CONTINUOUS_MODE
+ select MAINBOARD_USES_FSP2_0
+ select SPD_READ_BY_WORD
+ select NO_FIXED_XIP_ROM_SIZE
+ select FSP_M_XIP
+ select SUPERIO_ITE_IT8786E
+ select MAINBOARD_HAS_LPC_TPM
+
+if BOARD_LIBRETREND_BASEBOARD_LT1000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAINBOARD_VENDOR
+ string
+ default "Libretrend"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "LT1000" if BOARD_LIBRETREND_LT1000
+
+config MAINBOARD_DIR
+ string
+ default "libretrend/lt1000"
+
+config DEVICETREE
+ string
+ default "devicetree.cb"
+
+config MAX_CPUS
+ int
+ default 8
+
+config NO_POST
+ def_bool y
+ help
+ This platform does not have any way to see POST codes
+ so disable them by default.
+
+config VGA_BIOS_ID
+ string
+ default "8086,1916"
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config CPU_MICROCODE_CBFS_LEN
+ hex
+ default 0x18000
+
+config CPU_MICROCODE_CBFS_LOC
+ hex
+ default 0xFFE115A0
+
+config CBFS_SIZE
+ hex
+ default 0x5c0000
+
+endif
diff --git a/src/mainboard/libretrend/lt1000/Kconfig.name b/src/mainboard/libretrend/lt1000/Kconfig.name
new file mode 100644
index 0000000..4f599e5
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/Kconfig.name
@@ -0,0 +1,3 @@
+config BOARD_LIBRETREND_LT1000
+ bool "LT1000"
+ select BOARD_LIBRETREND_BASEBOARD_LT1000
diff --git a/src/mainboard/libretrend/lt1000/Makefile.inc b/src/mainboard/libretrend/lt1000/Makefile.inc
new file mode 100644
index 0000000..dbd661a
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/Makefile.inc
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += pei_data.c
+
+ramstage-y += pei_data.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+
+cbfs-files-y += etc/boot-menu-wait
+etc/boot-menu-wait-file := boot-menu-wait
+etc/boot-menu-wait-type := raw
diff --git a/src/mainboard/libretrend/lt1000/acpi/ec.asl b/src/mainboard/libretrend/lt1000/acpi/ec.asl
new file mode 100644
index 0000000..3991eec
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/acpi/ec.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Libretrend LDA
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <ec/libretrend/lt1000/acpi/ec.asl>
diff --git a/src/mainboard/libretrend/lt1000/acpi/mainboard.asl b/src/mainboard/libretrend/lt1000/acpi/mainboard.asl
new file mode 100644
index 0000000..c85be25
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/acpi/mainboard.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Libretrend LDA
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (Zero)
+ }
+
+ Method (_LID, 0, NotSerialized)
+ {
+ Return (One)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ Name (PBST, One)
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+ }
+
+ Device (SLPB)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+ Name (_STA, 0x0B)
+ }
+}
diff --git a/src/mainboard/libretrend/lt1000/acpi/superio.asl b/src/mainboard/libretrend/lt1000/acpi/superio.asl
new file mode 100644
index 0000000..92c272e
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/acpi/superio.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/libretrend/lt1000/acpi_tables.c b/src/mainboard/libretrend/lt1000/acpi_tables.c
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/acpi_tables.c
diff --git a/src/mainboard/libretrend/lt1000/board_info.txt b/src/mainboard/libretrend/lt1000/board_info.txt
new file mode 100644
index 0000000..2d7c893
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: Libretrend
+Board name: LT1000
+Category: desktop
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2018
diff --git a/src/mainboard/libretrend/lt1000/boot-menu-wait b/src/mainboard/libretrend/lt1000/boot-menu-wait
new file mode 100644
index 0000000..b1dea8d
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/boot-menu-wait
Binary files differ
diff --git a/src/mainboard/libretrend/lt1000/bootorder b/src/mainboard/libretrend/lt1000/bootorder
new file mode 100644
index 0000000..a1d6b0e
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/bootorder
@@ -0,0 +1 @@
+/pci at i0cf8/*@17/drive at 2/disk at 0
\ No newline at end of file
diff --git a/src/mainboard/libretrend/lt1000/bootsplash.jpg b/src/mainboard/libretrend/lt1000/bootsplash.jpg
new file mode 100644
index 0000000..dbcf873
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/bootsplash.jpg
Binary files differ
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
new file mode 100644
index 0000000..864817a
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -0,0 +1,316 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ register "eist_enable" = "1"
+ register "VmxEnable" = "1"
+
+ # Set the Thermal Control Circuit (TCC) activaction value to 95C
+ # even though FSP integration guide says to set it to 100C for SKL-U
+ # (offset at 0), because when the TCC activates at 100C, the CPU
+ # will have already shut itself down from overheating protection.
+ register "tcc_offset" = "5" # TCC of 95C
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f
+ register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef
+ register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff
+ register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Disable DPTF
+ register "dptf_enable" = "0"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "1"
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[0]" = "0"
+ register "SataPortsDevSlp[1]" = "0"
+ register "SataPortsDevSlp[2]" = "0"
+ register "SataSpeedLimit" = "2"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "0"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "PttSwitch" = "0"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "1"
+ register "SaGv" = "3"
+ register "SerialIrqConfigSirqEnable" = "1"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "0"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |
+ #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm |
+ #+----------------+-----------+-----------+-------------+----------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(7),
+ .voltage_limit = 1520,
+ .ac_loadline = 1500,
+ .dc_loadline = 1430,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
+ .ac_loadline = 570,
+ .dc_loadline = 483,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ .ac_loadline = 520,
+ .dc_loadline = 420,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ .ac_loadline = 520,
+ .dc_loadline = 420,
+ }"
+
+ # Enable Root Ports 3, 5 and 9
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpEnable[8]" = "1"
+ # Enable CLKREQ# for RP9
+ register "PcieRpClkReqSupport[8]" = "0"
+ # ClkReq for NVMe - Bruteforced (no other value works)
+ register "PcieRpClkReqNumber[8]" = "2"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right)
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right)
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # WiFi
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left)
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left)
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # GL850G for F_USB1 and F_USB2 headers
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right)
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right)
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header
+
+ # PL2 override 25W
+ register "tdp_pl2_override" = "25"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 on end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 on end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1f.0 on
+ chip ec/libretrend/lt1000
+ device pnp 0c09.0 on end
+ end
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ chip superio/ite/it8786e
+ register "TMPIN1.mode" = "THERMAL_PECI"
+ register "TMPIN1.offset" = "100"
+ register "TMPIN1.min" = "128"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.min" = "128"
+ register "ec.vin_mask" = "VIN_ALL"
+ register "ec.smbus_en" = "1"
+ # FAN1 is CPU fan (on board)
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN1.smart.tmpin" = " 1"
+ register "FAN1.smart.tmp_off" = "35"
+ register "FAN1.smart.tmp_start" = "60"
+ register "FAN1.smart.tmp_full" = "85"
+ register "FAN1.smart.tmp_delta" = " 2"
+ register "FAN1.smart.pwm_start" = "40"
+ register "FAN1.smart.slope" = "24"
+ # FAN2 is system fan (4 pin connector populated)
+ #register "FAN2.mode" = "FAN_MODE_OFF"
+ # FAN3 PWM is used for LVDS
+ #register "FAN3.mode" = "FAN_MODE_OFF"
+
+ device pnp 2e.0 off end
+ device pnp 2e.1 on # COM 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 on # COM 2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Printer Port
+ io 0x60 = 0x378
+ io 0x62 = 0x778
+ irq 0x70 = 5
+ drq 0x74 = 3
+ irq 0xf0 = 0x0b
+ end
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0xa40
+ io 0x62 = 0xa30
+ irq 0x70 = 9
+ irq 0xf0 = 0x80 # clear 3VSB off bit
+ irq 0xf1 = 0x40
+ end
+ device pnp 2e.5 on # Keyboard, turn off ?
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 on # Mouse, turn off ?
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 off # GPIO
+ end
+ device pnp 2e.8 off # COM 3
+ io 0x60 = 0x3e8
+ irq 0x70 = 7
+ irq 0xf0 = 0x01
+ irq 0xf1 = 0x53
+ end
+ device pnp 2e.9 off # COM 4
+ io 0x60 = 0x2e8
+ irq 0x70 = 7
+ irq 0xf0 = 0x01
+ irq 0xf1 = 0x53
+ end
+ device pnp 2e.a off end # CIR
+ device pnp 2e.b off # COM 5
+ io 0x60 = 0x2f0
+ irq 0x70 = 7
+ irq 0xf0 = 0x01
+ irq 0xf1 = 0x53
+ end
+ device pnp 2e.c off # COM 6
+ io 0x60 = 0x2e0
+ irq 0x70 = 7
+ irq 0xf0 = 0x01
+ irq 0xf1 = 0x53
+ end
+ end
+ end # LPC Interface
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/libretrend/lt1000/dsdt.asl b/src/mainboard/libretrend/lt1000/dsdt.asl
new file mode 100644
index 0000000..1bf202e
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/dsdt.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/skylake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ }
+
+ // Chipset specific sleep states
+ #include <soc/intel/skylake/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/libretrend/lt1000/hda_verb.c b/src/mainboard/libretrend/lt1000/hda_verb.c
new file mode 100644
index 0000000..e8eecdf
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/hda_verb.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation
+ * (Written by Naresh G Solanki <naresh.solanki at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootstate.h>
+#include <chip.h>
+#include <console/console.h>
+#include <device/azalia_device.h>
+#include <soc/intel/common/hda_verb.h>
+#include <soc/pci_devs.h>
+
+#include "hda_verb.h"
+
+static void codecs_init(u8 *base, u32 codec_mask)
+{
+ int i;
+
+ /* Can support up to 4 codecs */
+ for (i = 3; i >= 0; i--) {
+ if (codec_mask & (1 << i))
+ hda_codec_init(base, i, cim_verb_data_size,
+ cim_verb_data);
+ }
+
+ if (pc_beep_verbs_size)
+ hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
+}
+
+static void mb_hda_codec_init(void *unused)
+{
+ static struct soc_intel_skylake_config *config;
+ u8 *base;
+ struct resource *res;
+ u32 codec_mask;
+ struct device *dev;
+
+ dev = SA_DEV_ROOT;
+ /* Check if HDA is enabled, else return */
+ if (dev == NULL || dev->chip_info == NULL)
+ return;
+
+ config = dev->chip_info;
+
+ /*
+ * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port,
+ * 3:I2S Ports. In HDA mode where codec need to be programmed with
+ * verb table
+ */
+ if (config->IoBufferOwnership == 3)
+ return;
+
+ /* Find base address */
+ dev = dev_find_slot(0, PCH_DEVFN_HDA);
+ if (dev == NULL)
+ return;
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!res)
+ return;
+
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "HDA: base = %p\n", base);
+
+ codec_mask = hda_codec_detect(base);
+
+ if (codec_mask) {
+ printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask);
+ codecs_init(base, codec_mask);
+ }
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL);
diff --git a/src/mainboard/libretrend/lt1000/hda_verb.h b/src/mainboard/libretrend/lt1000/hda_verb.h
new file mode 100644
index 0000000..660ad0c
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/hda_verb.h
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */
+ 0x19910269, /* Subsystem ID */
+ 0x0000000c, /* Number of jacks (NID entries) */
+
+ 0x0017ff00, /* Function Reset */
+ 0x0017ff00, /* Double Function Reset */
+ 0x0017ff00,
+ 0x0017ff00,
+
+ /* Bits 31:28 - Codec Address */
+ /* Bits 27:20 - NID */
+ /* Bits 19:8 - Verb ID */
+ /* Bits 7:0 - Payload */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */
+ AZALIA_SUBVENDOR(0x0, 0x19910269),
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x12) */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x40000000),
+
+ /* Pin Complex (NID 0x14) */
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+
+ /* Pin Complex (NID 0x15) */
+ AZALIA_PIN_CFG(0x0, 0x15, 0x04214020),
+
+ /* Pin Complex (NID 0x17) */
+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+
+ /* Pin Complex (NID 0x18) */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x04a19040),
+
+ /* Pin Complex (NID 0x19) */
+ AZALIA_PIN_CFG(0x0, 0x19, 0x90a70130),
+
+ /* Pin Complex (NID 0x1A) */
+ AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
+
+ /* Pin Complex (NID 0x1B) */
+ AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
+
+ /* Pin Complex (NID 0x1D) */
+ AZALIA_PIN_CFG(0x0, 0x1D, 0x40548505),
+
+ /* Pin Complex (NID 0x1E) */
+ AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[] = {
+};
+AZALIA_ARRAY_SIZES;
+#endif
diff --git a/src/mainboard/libretrend/lt1000/mainboard.c b/src/mainboard/libretrend/lt1000/mainboard.c
new file mode 100644
index 0000000..462b995
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/mainboard.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Purism SPC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <smbios.h>
+#include <string.h>
+#include <cbfs.h>
+
+#define MAX_SERIAL_LENGTH 0x100
+
+const char *smbios_mainboard_serial_number(void)
+{
+ static char serial_number[MAX_SERIAL_LENGTH + 1] = {0};
+ struct cbfsf file;
+
+ if (serial_number[0] != 0)
+ return serial_number;
+
+ if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) {
+ struct region_device cbfs_region;
+ size_t serial_len;
+
+ cbfs_file_data(&cbfs_region, &file);
+
+ serial_len = region_device_sz(&cbfs_region);
+ if (serial_len <= MAX_SERIAL_LENGTH) {
+ if (rdev_readat(&cbfs_region, serial_number, 0,
+ serial_len) == serial_len) {
+ serial_number[serial_len] = 0;
+ return serial_number;
+ }
+ }
+ }
+
+ strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER,
+ MAX_SERIAL_LENGTH);
+
+ return serial_number;
+}
diff --git a/src/mainboard/libretrend/lt1000/mainboard_gpio.h b/src/mainboard/libretrend/lt1000/mainboard_gpio.h
new file mode 100644
index 0000000..c493f3e
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/mainboard_gpio.h
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
+/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
+/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
+/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+/* PIRQA# */ PAD_CFG_NC(GPP_A7),
+/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+/* PME# */ PAD_CFG_NC(GPP_A11),
+/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
+/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+/* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
+/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
+/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+/* ISH_GP0 */ PAD_CFG_GPI(GPP_A18, NONE, DEEP),
+/* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+/* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP),
+/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
+/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
+
+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
+/* VRALERT# */ PAD_CFG_NC(GPP_B2),
+/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),
+/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
+/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),
+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
+/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16),
+/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),
+/* GSPI0_MOSI */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
+/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),
+/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),
+/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),
+/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
+/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
+
+/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+/* SMBDATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
+/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
+/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP),
+/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */
+/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */
+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+/* UART1_RXD */ PAD_CFG_NC(GPP_C12),
+/* UART1_TXD */ PAD_CFG_NC(GPP_C13),
+/* UART1_RTS# */ PAD_CFG_NC(GPP_C14),
+/* UART1_CTS# */ PAD_CFG_NC(GPP_C15),
+/* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP),
+/* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP),
+/* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP),
+/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),
+/* UART2_RXD */ PAD_CFG_NC(GPP_C20),
+/* UART2_TXD */ PAD_CFG_NC(GPP_C21),
+/* UART2_RTS# */ PAD_CFG_NC(GPP_C22),
+/* UART2_CTS# */ PAD_CFG_NC(GPP_C23),
+
+/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),
+/* SPI1_CLK */ PAD_CFG_NC(GPP_D1),
+/* SPI1_MISO */ PAD_CFG_NC(GPP_D2),
+/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),
+/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
+/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),
+/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
+/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
+/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
+/* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP),
+/* ISH_SPI_CLK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),
+/* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP),
+/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),
+/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
+/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
+/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
+/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),
+/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22),
+/* I2S_MCLK */ PAD_CFG_NC(GPP_D23),
+
+/* SATAXPCI0 */ PAD_CFG_NC(GPP_E0),
+/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
+/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
+/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
+/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
+/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
+/* CPU_GP1 */ PAD_CFG_NC(GPP_E7),
+/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+/* USB2_OC3# */ PAD_CFG_NC(GPP_E12),
+/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15),
+/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NONE),
+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
+/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
+/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
+/* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP),
+
+/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),
+/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),
+/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),
+/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),
+/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
+/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
+/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
+/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
+/* I2C5_SDA */ PAD_CFG_NC(GPP_F10),
+/* I2C5_SCL */ PAD_CFG_NC(GPP_F11),
+/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),
+/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),
+/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),
+/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),
+/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),
+/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),
+/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),
+/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),
+/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),
+/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),
+/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),
+/* RSVD */ PAD_CFG_NC(GPP_F23),
+
+/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
+/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
+/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
+/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1),
+
+/* BATLOW# */ PAD_CFG_NC(GPD0),
+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
+/* LAN_WAKE# */ PAD_CFG_NC(GPD2),
+/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+/* RSVD */ PAD_CFG_NC(GPD7),
+/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/libretrend/lt1000/pei_data.c b/src/mainboard/libretrend/lt1000/pei_data.c
new file mode 100644
index 0000000..0be917d
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/pei_data.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2017 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include "pei_data.h"
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr)
+{
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
+{
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map[2][8] = {
+ { 0, 1, 3, 2, 4, 5, 6, 7 },
+ { 1, 0, 4, 5, 2, 3, 6, 7 } };
+ memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
+}
+
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 121, 81, 100 };
+ memcpy(rcomp_ptr, RcompResistor,
+ sizeof(RcompResistor));
+}
+
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ /* Rcomp target */
+ const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ mainboard_fill_dq_map_data(&pei_data->dq_map);
+ mainboard_fill_dqs_map_data(&pei_data->dqs_map);
+ mainboard_fill_rcomp_res_data(&pei_data->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget);
+}
diff --git a/src/mainboard/libretrend/lt1000/pei_data.h b/src/mainboard/libretrend/lt1000/pei_data.h
new file mode 100644
index 0000000..320d980
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/pei_data.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MAINBOARD_PEI_DATA_H_
+#define _MAINBOARD_PEI_DATA_H_
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr);
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
+
+#endif
diff --git a/src/mainboard/libretrend/lt1000/ramstage.c b/src/mainboard/libretrend/lt1000/ramstage.c
new file mode 100644
index 0000000..64381d5
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "mainboard_gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/libretrend/lt1000/romstage.c b/src/mainboard/libretrend/lt1000/romstage.c
new file mode 100644
index 0000000..3cccdee
--- /dev/null
+++ b/src/mainboard/libretrend/lt1000/romstage.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2017 Purism SPC.
+ * Copyright (C) 2018 Libretrend LDA
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <soc/romstage.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8786e/it8786e.h>
+#include <spd_bin.h>
+#include <console/console.h>
+#include <build.h>
+#include <config.h>
+#include "pei_data.h"
+
+
+#define SERIAL1_DEV PNP_DEV(0x2e, IT8786E_SP1)
+
+extern char coreboot_version[];
+
+static const char* get_mainboard_bios_version(void)
+{
+ if (strlen(CONFIG_LOCALVERSION))
+ return CONFIG_LOCALVERSION;
+ else
+ return coreboot_version;
+}
+
+void car_mainboard_pre_console_init(void)
+{
+ ite_conf_clkin(SERIAL1_DEV, ITE_UART_CLK_PREDIVIDE_24);
+ ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ mem_cfg = &mupd->FspmConfig;
+
+ struct spd_block blk = {
+ .addr_map = { 0x50, 0x52, },
+ };
+
+ printk(BIOS_ALERT, CONFIG_MAINBOARD_VENDOR " "
+ CONFIG_MAINBOARD_PART_NUMBER "\n");
+ printk(BIOS_ALERT, "coreboot build %s\n", COREBOOT_DMI_DATE);
+ printk(BIOS_ALERT, "BIOS version %s\n", get_mainboard_bios_version());
+
+ get_spd_smbus(&blk);
+
+ /* At least 1 SPD has to be retrieved from DIMM slots.
+ * Assert when no DIMMs in the system.
+ */
+ assert(blk.spd_array[0][0] != 0 || blk.spd_array[1][0] != 0)
+
+ dump_spd_info(&blk);
+
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ mem_cfg->DqPinsInterleaved = 1;
+ mem_cfg->SmbusEnable = 1;
+ mem_cfg->PchSmbusIoBase = 0xf040;
+ mem_cfg->MemorySpdDataLen = blk.len;
+ if (blk.spd_array[0][0] != 0)
+ mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+ if (blk.spd_array[1][0] != 0)
+ mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1];
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab
Gerrit-Change-Number: 30360
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski <michal.zygowski at 3mdeb.com>
Gerrit-MessageType: newchange
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