<p>Michał Żygowski has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30360">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/mainboard/libretrend/lt1000: Initial commit<br><br>Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab<br>Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com><br>---<br>A src/ec/libretrend/lt1000/Kconfig<br>A src/ec/libretrend/lt1000/acpi/battery.asl<br>A src/ec/libretrend/lt1000/acpi/ec.asl<br>A src/mainboard/libretrend/Kconfig<br>A src/mainboard/libretrend/Kconfig.name<br>A src/mainboard/libretrend/lt1000/Kconfig<br>A src/mainboard/libretrend/lt1000/Kconfig.name<br>A src/mainboard/libretrend/lt1000/Makefile.inc<br>A src/mainboard/libretrend/lt1000/acpi/ec.asl<br>A src/mainboard/libretrend/lt1000/acpi/mainboard.asl<br>A src/mainboard/libretrend/lt1000/acpi/superio.asl<br>A src/mainboard/libretrend/lt1000/acpi_tables.c<br>A src/mainboard/libretrend/lt1000/board_info.txt<br>A src/mainboard/libretrend/lt1000/boot-menu-wait<br>A src/mainboard/libretrend/lt1000/bootorder<br>A src/mainboard/libretrend/lt1000/bootsplash.jpg<br>A src/mainboard/libretrend/lt1000/devicetree.cb<br>A src/mainboard/libretrend/lt1000/dsdt.asl<br>A src/mainboard/libretrend/lt1000/hda_verb.c<br>A src/mainboard/libretrend/lt1000/hda_verb.h<br>A src/mainboard/libretrend/lt1000/mainboard.c<br>A src/mainboard/libretrend/lt1000/mainboard_gpio.h<br>A src/mainboard/libretrend/lt1000/pei_data.c<br>A src/mainboard/libretrend/lt1000/pei_data.h<br>A src/mainboard/libretrend/lt1000/ramstage.c<br>A src/mainboard/libretrend/lt1000/romstage.c<br>26 files changed, 1,314 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/30360/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/ec/libretrend/lt1000/Kconfig b/src/ec/libretrend/lt1000/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..269dbfc</span><br><span>--- /dev/null</span><br><span>+++ b/src/ec/libretrend/lt1000/Kconfig</span><br><span>@@ -0,0 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config EC_LIBRETREND_LT1000</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Libretrend EC</span><br><span>diff --git a/src/ec/libretrend/lt1000/acpi/battery.asl b/src/ec/libretrend/lt1000/acpi/battery.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..4e3d11d</span><br><span>--- /dev/null</span><br><span>+++ b/src/ec/libretrend/lt1000/acpi/battery.asl</span><br><span>@@ -0,0 +1,57 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Libretrend LDA</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (BAT0)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0C0A"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, Zero)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Zero)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (BAT1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0C0A"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, One)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Zero)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_BST, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (BST1 ())</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (BAT2)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0C0A"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Zero)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_BST, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (BST2 ())</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/ec/libretrend/lt1000/acpi/ec.asl b/src/ec/libretrend/lt1000/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..96367e6</span><br><span>--- /dev/null</span><br><span>+++ b/src/ec/libretrend/lt1000/acpi/ec.asl</span><br><span>@@ -0,0 +1,55 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Libretrend LDA</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (EC)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0C09"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, One)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized) // _STA: Status</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Zero)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (B1ST, 0x32)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (B2ST, 0x36)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (BST1, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (PKG1, Package (0x04)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Zero,</span><br><span style="color: hsl(120, 100%, 40%);">+ Zero,</span><br><span style="color: hsl(120, 100%, 40%);">+ Zero,</span><br><span style="color: hsl(120, 100%, 40%);">+ Zero</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (PKG1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (BST2, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (PKG2, Package (0x04)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Zero,</span><br><span style="color: hsl(120, 100%, 40%);">+ Zero,</span><br><span style="color: hsl(120, 100%, 40%);">+ Zero,</span><br><span style="color: hsl(120, 100%, 40%);">+ Zero</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (PKG2)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "battery.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/libretrend/Kconfig b/src/mainboard/libretrend/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..a60995a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/Kconfig</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Libretrend LDA</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if VENDOR_LIBRETREND</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+choice</span><br><span style="color: hsl(120, 100%, 40%);">+ prompt "Mainboard model"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+source "src/mainboard/libretrend/*/Kconfig.name"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endchoice</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+source "src/mainboard/libretrend/*/Kconfig"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_VENDOR</span><br><span style="color: hsl(120, 100%, 40%);">+ string "Mainboard Vendor"</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Libretrend"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # VENDOR_LIBRETREND</span><br><span>diff --git a/src/mainboard/libretrend/Kconfig.name b/src/mainboard/libretrend/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..cd272b0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config VENDOR_LIBRETREND</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Libretrend"</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/Kconfig b/src/mainboard/libretrend/lt1000/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..c4e2ccd</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/Kconfig</span><br><span>@@ -0,0 +1,71 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_LIBRETREND_BASEBOARD_LT1000</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool n</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_8192</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_SKYLAKE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SERIRQ_CONTINUOUS_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_USES_FSP2_0</span><br><span style="color: hsl(120, 100%, 40%);">+ select SPD_READ_BY_WORD</span><br><span style="color: hsl(120, 100%, 40%);">+ select NO_FIXED_XIP_ROM_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ select FSP_M_XIP</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_ITE_IT8786E</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_LPC_TPM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_LIBRETREND_BASEBOARD_LT1000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config IRQ_SLOT_COUNT</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 18</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_VENDOR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Libretrend"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "LT1000" if BOARD_LIBRETREND_LT1000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "libretrend/lt1000"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "devicetree.cb"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config NO_POST</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This platform does not have any way to see POST codes</span><br><span style="color: hsl(120, 100%, 40%);">+ so disable them by default.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VGA_BIOS_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "8086,1916"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DIMM_MAX</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DIMM_SPD_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 512</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CPU_MICROCODE_CBFS_LEN</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x18000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CPU_MICROCODE_CBFS_LOC</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xFFE115A0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CBFS_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x5c0000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/Kconfig.name b/src/mainboard/libretrend/lt1000/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..4f599e5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/Kconfig.name</span><br><span>@@ -0,0 +1,3 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_LIBRETREND_LT1000</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "LT1000"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_LIBRETREND_BASEBOARD_LT1000</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/Makefile.inc b/src/mainboard/libretrend/lt1000/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..dbd661a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/Makefile.inc</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += pei_data.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += pei_data.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += ramstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += hda_verb.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+cbfs-files-y += etc/boot-menu-wait</span><br><span style="color: hsl(120, 100%, 40%);">+etc/boot-menu-wait-file := boot-menu-wait</span><br><span style="color: hsl(120, 100%, 40%);">+etc/boot-menu-wait-type := raw</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/acpi/ec.asl b/src/mainboard/libretrend/lt1000/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..3991eec</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/acpi/ec.asl</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Libretrend LDA</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/libretrend/lt1000/acpi/ec.asl></span><br><span>diff --git a/src/mainboard/libretrend/lt1000/acpi/mainboard.asl b/src/mainboard/libretrend/lt1000/acpi/mainboard.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..c85be25</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/acpi/mainboard.asl</span><br><span>@@ -0,0 +1,49 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Libretrend LDA</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Scope (\_SB)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (LID0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0C0D"))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Zero)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_LID, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (One)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PWRB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0C0C"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (PBST, One)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, NotSerialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x0F)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (SLPB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0C0E"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_STA, 0x0B)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/acpi/superio.asl b/src/mainboard/libretrend/lt1000/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..92c272e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/acpi/superio.asl</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/pc80/pc/ps2_controller.asl></span><br><span>diff --git a/src/mainboard/libretrend/lt1000/acpi_tables.c b/src/mainboard/libretrend/lt1000/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/acpi_tables.c</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/board_info.txt b/src/mainboard/libretrend/lt1000/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..2d7c893</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/board_info.txt</span><br><span>@@ -0,0 +1,8 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor name: Libretrend</span><br><span style="color: hsl(120, 100%, 40%);">+Board name: LT1000</span><br><span style="color: hsl(120, 100%, 40%);">+Category: desktop</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: SOIC8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2018</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/boot-menu-wait b/src/mainboard/libretrend/lt1000/boot-menu-wait</span><br><span>new file mode 100644</span><br><span>index 0000000..b1dea8d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/boot-menu-wait</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/bootorder b/src/mainboard/libretrend/lt1000/bootorder</span><br><span>new file mode 100644</span><br><span>index 0000000..a1d6b0e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/bootorder</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/pci@i0cf8/*@17/drive@2/disk@0</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/bootsplash.jpg b/src/mainboard/libretrend/lt1000/bootsplash.jpg</span><br><span>new file mode 100644</span><br><span>index 0000000..dbcf873</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/bootsplash.jpg</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..864817a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/devicetree.cb</span><br><span>@@ -0,0 +1,316 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/skylake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable deep Sx states</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s3_enable_ac" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s3_enable_dc" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s5_enable_ac" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s5_enable_dc" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eist_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "VmxEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set the Thermal Control Circuit (TCC) activaction value to 95C</span><br><span style="color: hsl(120, 100%, 40%);">+ # even though FSP integration guide says to set it to 100C for SKL-U</span><br><span style="color: hsl(120, 100%, 40%);">+ # (offset at 0), because when the TCC activates at 100C, the CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ # will have already shut itself down from overheating protection.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tcc_offset" = "5" # TCC of 95C</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "GPP_C"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "GPP_D"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "GPP_E"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable "Intel Speed Shift Technology"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Disable DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dptf_enable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ProbelessTrace" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableLan" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableSata" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSalpSupport" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataMode" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[0]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[1]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[2]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSpeedLimit" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableAzalia" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DspEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "IoBufferOwnership" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableTraceHub" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SsicPortEnable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SmbusEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Cio2Enable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcEnabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcHs400Enabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsSdCardEnabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PttSwitch" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "InternalGfx" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SkipExtGfxScan" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Device4Enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "HeciEnabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIrqConfigSirqEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS3MinAssert" = "2" # 50ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS4MinAssert" = "1" # 1s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpSusMinAssert" = "3" # 500ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpAMinAssert" = "3" # 2s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmTimerDisabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # VR Settings Configuration for 4 Domains</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-----------+-----------+-------------+----------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Domain/Setting | SA | IA | GT Unsliced | GT |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-----------+-----------+-------------+----------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi1Threshold | 20A | 20A | 20A | 20A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi2Threshold | 4A | 5A | 5A | 5A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi3Threshold | 1A | 1A | 1A | 1A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi3Enable | 1 | 1 | 1 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi4Enable | 1 | 1 | 1 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| ImonSlope | 0 | 0 | 0 | 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| ImonOffset | 0 | 0 | 0 | 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| IccMax | 7A | 34A | 35A | 35A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-----------+-----------+-------------+----------+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(4),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(7),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ac_loadline = 1500,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dc_loadline = 1430,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_IA_CORE]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(34),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ac_loadline = 570,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dc_loadline = 483,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_GT_UNSLICED]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(35),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ac_loadline = 520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dc_loadline = 420,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_GT_SLICED]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(35),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ac_loadline = 520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dc_loadline = 420,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Root Ports 3, 5 and 9</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable CLKREQ# for RP9</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[8]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ # ClkReq for NVMe - Bruteforced (no other value works)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[8]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # WiFi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # GL850G for F_USB1 and F_USB2 headers</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PL2 override 25W</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tdp_pl2_override" = "25"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Send an extra VR mailbox command for the PS4 exit issue</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SendVrMbxCmd" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Lock Down</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 on end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.2 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCI Express Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCI Express Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCI Express Port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCI Express Port 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCI Express Port 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 off end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/libretrend/lt1000</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c09.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/ite/it8786e</span><br><span style="color: hsl(120, 100%, 40%);">+ register "TMPIN1.mode" = "THERMAL_PECI"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "TMPIN1.offset" = "100"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "TMPIN1.min" = "128"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "TMPIN2.mode" = "THERMAL_RESISTOR"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "TMPIN2.min" = "128"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ec.vin_mask" = "VIN_ALL"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ec.smbus_en" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # FAN1 is CPU fan (on board)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.tmpin" = " 1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.tmp_off" = "35"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.tmp_start" = "60"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.tmp_full" = "85"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.tmp_delta" = " 2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.pwm_start" = "40"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.slope" = "24"</span><br><span style="color: hsl(120, 100%, 40%);">+ # FAN2 is system fan (4 pin connector populated)</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "FAN2.mode" = "FAN_MODE_OFF"</span><br><span style="color: hsl(120, 100%, 40%);">+ # FAN3 PWM is used for LVDS</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "FAN3.mode" = "FAN_MODE_OFF"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 on # COM 1</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 on # COM 2</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x2f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 on # Printer Port</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x378</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x778</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 5</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x0b</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.4 on # Environment Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0xa40</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0xa30</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 9</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x80 # clear 3VSB off bit</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf1 = 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # Keyboard, turn off ?</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 on # Mouse, turn off ?</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 12</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 off # GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 off # COM 3</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3e8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf1 = 0x53</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.9 off # COM 4</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x2e8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf1 = 0x53</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a off end # CIR</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.b off # COM 5</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x2f0</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x01 </span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf1 = 0x53</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.c off # COM 6</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x2e0</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf1 = 0x53</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 off end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/dsdt.asl b/src/mainboard/libretrend/lt1000/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..1bf202e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/dsdt.asl</span><br><span>@@ -0,0 +1,51 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02, // DSDT revision: ACPI v2.0 and up</span><br><span style="color: hsl(120, 100%, 40%);">+ OEM_ID,</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_TABLE_CREATOR,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20110725 // OEM revision</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // Some generic macros</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/skylake/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // global NVS and variables</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/skylake/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/intel/common/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/skylake/acpi/systemagent.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/skylake/acpi/pch.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Chipset specific sleep states</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/skylake/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Mainboard specific</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/mainboard.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/hda_verb.c b/src/mainboard/libretrend/lt1000/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e8eecdf</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/hda_verb.c</span><br><span>@@ -0,0 +1,83 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ * (Written by Naresh G Solanki <naresh.solanki@intel.com> for Intel Corp.)</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootstate.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/hda_verb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "hda_verb.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void codecs_init(u8 *base, u32 codec_mask)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Can support up to 4 codecs */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 3; i >= 0; i--) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (codec_mask & (1 << i))</span><br><span style="color: hsl(120, 100%, 40%);">+ hda_codec_init(base, i, cim_verb_data_size,</span><br><span style="color: hsl(120, 100%, 40%);">+ cim_verb_data);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pc_beep_verbs_size)</span><br><span style="color: hsl(120, 100%, 40%);">+ hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mb_hda_codec_init(void *unused)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static struct soc_intel_skylake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *base;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct resource *res;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 codec_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Check if HDA is enabled, else return */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev == NULL || dev->chip_info == NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port,</span><br><span style="color: hsl(120, 100%, 40%);">+ * 3:I2S Ports. In HDA mode where codec need to be programmed with</span><br><span style="color: hsl(120, 100%, 40%);">+ * verb table</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->IoBufferOwnership == 3)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Find base address */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, PCH_DEVFN_HDA);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev == NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ res = find_resource(dev, PCI_BASE_ADDRESS_0);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!res)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ base = res2mmio(res, 0, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "HDA: base = %p\n", base);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ codec_mask = hda_codec_detect(base);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (codec_mask) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask);</span><br><span style="color: hsl(120, 100%, 40%);">+ codecs_init(base, codec_mask);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL);</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/hda_verb.h b/src/mainboard/libretrend/lt1000/hda_verb.h</span><br><span>new file mode 100644</span><br><span>index 0000000..660ad0c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/hda_verb.h</span><br><span>@@ -0,0 +1,76 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef HDA_VERB_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDA_VERB_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* coreboot specific header */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x19910269, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000000c, /* Number of jacks (NID entries) */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0017ff00, /* Function Reset */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0017ff00, /* Double Function Reset */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0017ff00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0017ff00,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bits 31:28 - Codec Address */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bits 27:20 - NID */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bits 19:8 - Verb ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bits 7:0 - Payload */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(0x0, 0x19910269),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Widget Verb Table */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x12) */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x12, 0x40000000),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x14) */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x15) */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x15, 0x04214020),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x17) */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x18) */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x18, 0x04a19040),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x19) */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x19, 0x90a70130),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1A) */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1B) */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1D) */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1D, 0x40548505),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Complex (NID 0x1E) */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+AZALIA_ARRAY_SIZES;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/mainboard.c b/src/mainboard/libretrend/lt1000/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..462b995</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/mainboard.c</span><br><span>@@ -0,0 +1,50 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Purism SPC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <smbios.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbfs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_SERIAL_LENGTH 0x100</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const char *smbios_mainboard_serial_number(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static char serial_number[MAX_SERIAL_LENGTH + 1] = {0};</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cbfsf file;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (serial_number[0] != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return serial_number;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct region_device cbfs_region;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t serial_len;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cbfs_file_data(&cbfs_region, &file);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ serial_len = region_device_sz(&cbfs_region);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (serial_len <= MAX_SERIAL_LENGTH) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (rdev_readat(&cbfs_region, serial_number, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ serial_len) == serial_len) {</span><br><span style="color: hsl(120, 100%, 40%);">+ serial_number[serial_len] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ return serial_number;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_SERIAL_LENGTH);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return serial_number;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/mainboard_gpio.h b/src/mainboard/libretrend/lt1000/mainboard_gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..c493f3e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/mainboard_gpio.h</span><br><span>@@ -0,0 +1,201 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MAINBOARD_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpe.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Pad configuration in ramstage. */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PIRQA# */ PAD_CFG_NC(GPP_A7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PME# */ PAD_CFG_NC(GPP_A11),</span><br><span style="color: hsl(120, 100%, 40%);">+/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP0 */ PAD_CFG_GPI(GPP_A18, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* VRALERT# */ PAD_CFG_NC(GPP_B2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MOSI */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBDATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_RXD */ PAD_CFG_NC(GPP_C12),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_TXD */ PAD_CFG_NC(GPP_C13),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_RTS# */ PAD_CFG_NC(GPP_C14),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_CTS# */ PAD_CFG_NC(GPP_C15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RXD */ PAD_CFG_NC(GPP_C20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_TXD */ PAD_CFG_NC(GPP_C21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RTS# */ PAD_CFG_NC(GPP_C22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_CTS# */ PAD_CFG_NC(GPP_C23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_CLK */ PAD_CFG_NC(GPP_D1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_MISO */ PAD_CFG_NC(GPP_D2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* FASHTRIG */ PAD_CFG_NC(GPP_D4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CLK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S_MCLK */ PAD_CFG_NC(GPP_D23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCI0 */ PAD_CFG_NC(GPP_E0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP1 */ PAD_CFG_NC(GPP_E7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC3# */ PAD_CFG_NC(GPP_E12),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C5_SDA */ PAD_CFG_NC(GPP_F10),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C5_SCL */ PAD_CFG_NC(GPP_F11),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* RSVD */ PAD_CFG_NC(GPP_F23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* BATLOW# */ PAD_CFG_NC(GPD0),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAN_WAKE# */ PAD_CFG_NC(GPD2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* RSVD */ PAD_CFG_NC(GPD7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/pei_data.c b/src/mainboard/libretrend/lt1000/pei_data.c</span><br><span>new file mode 100644</span><br><span>index 0000000..0be917d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/pei_data.c</span><br><span>@@ -0,0 +1,65 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Purism SPC.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pei_data.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pei_wrapper.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "pei_data.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_dq_map_data(void *dq_map_ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQ byte map */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dq_map[2][12] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_dqs_map_data(void *dqs_map_ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQS CPU<>DRAM map */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map[2][8] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 1, 3, 2, 4, 5, 6, 7 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 4, 5, 2, 3, 6, 7 } };</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rcomp resistor */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u16 RcompResistor[3] = { 121, 81, 100 };</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(rcomp_ptr, RcompResistor,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(RcompResistor));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rcomp target */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_pei_data(struct pei_data *pei_data)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_dq_map_data(&pei_data->dq_map);</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_dqs_map_data(&pei_data->dqs_map);</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_rcomp_res_data(&pei_data->RcompResistor);</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/pei_data.h b/src/mainboard/libretrend/lt1000/pei_data.h</span><br><span>new file mode 100644</span><br><span>index 0000000..320d980</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/pei_data.h</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Purism SPC.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _MAINBOARD_PEI_DATA_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _MAINBOARD_PEI_DATA_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_dq_map_data(void *dq_map_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_dqs_map_data(void *dqs_map_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/ramstage.c b/src/mainboard/libretrend/lt1000/ramstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..64381d5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/ramstage.c</span><br><span>@@ -0,0 +1,25 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/ramstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "mainboard_gpio.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_silicon_init_params(FSP_SIL_UPD *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure pads prior to SiliconInit() in case there's any</span><br><span style="color: hsl(120, 100%, 40%);">+ * dependencies during hardware initialization. */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/libretrend/lt1000/romstage.c b/src/mainboard/libretrend/lt1000/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..3cccdee</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/libretrend/lt1000/romstage.c</span><br><span>@@ -0,0 +1,86 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2010 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Purism SPC.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Libretrend LDA</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/ite/common/ite.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/ite/it8786e/it8786e.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <spd_bin.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <build.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <config.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "pei_data.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIAL1_DEV PNP_DEV(0x2e, IT8786E_SP1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern char coreboot_version[];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const char* get_mainboard_bios_version(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (strlen(CONFIG_LOCALVERSION))</span><br><span style="color: hsl(120, 100%, 40%);">+ return CONFIG_LOCALVERSION;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ return coreboot_version;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void car_mainboard_pre_console_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_conf_clkin(SERIAL1_DEV, ITE_UART_CLK_PREDIVIDE_24);</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_memory_init_params(FSPM_UPD *mupd)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_M_CONFIG *mem_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg = &mupd->FspmConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ struct spd_block blk = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .addr_map = { 0x50, 0x52, },</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ALERT, CONFIG_MAINBOARD_VENDOR " "</span><br><span style="color: hsl(120, 100%, 40%);">+ CONFIG_MAINBOARD_PART_NUMBER "\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ALERT, "coreboot build %s\n", COREBOOT_DMI_DATE);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ALERT, "BIOS version %s\n", get_mainboard_bios_version());</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ get_spd_smbus(&blk);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* At least 1 SPD has to be retrieved from DIMM slots.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Assert when no DIMMs in the system.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(blk.spd_array[0][0] != 0 || blk.spd_array[1][0] != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dump_spd_info(&blk);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->DqPinsInterleaved = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SmbusEnable = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->PchSmbusIoBase = 0xf040;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->MemorySpdDataLen = blk.len;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (blk.spd_array[0][0] != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];</span><br><span style="color: hsl(120, 100%, 40%);">+ if (blk.spd_array[1][0] != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1];</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30360">change 30360</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30360"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab </div>
<div style="display:none"> Gerrit-Change-Number: 30360 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Michał Żygowski <michal.zygowski@3mdeb.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>