[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/broadwell: implement RMRR ACPI table

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30234 )

Change subject: soc/intel/broadwell: implement RMRR ACPI table
......................................................................

soc/intel/broadwell: implement RMRR ACPI table

Modeled after Skylake implementation; uses duplicated
intel common SA functions to get RMRR addresses

Test: build/boot purism/librem13v1, observe IOMMU fully functional
with intel_iommu=on kernel parameter

Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
Reviewed-on: https://review.coreboot.org/c/30234
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Nico Huber <nico.h at gmx.de>
---
M src/soc/intel/broadwell/acpi.c
M src/soc/intel/broadwell/include/soc/systemagent.h
M src/soc/intel/broadwell/systemagent.c
3 files changed, 24 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved



diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 9c6bd9b..42d31c8 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -590,12 +590,20 @@
 	/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
 	if (igfx_dev && igfx_dev->enabled && gfxvtbar
 			&& gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
-		const unsigned long tmp = current;
+		unsigned long tmp = current;
 
 		current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
 		current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 
 		acpi_dmar_drhd_fixup(tmp, current);
+
+		/* Add RMRR entry */
+		tmp = current;
+
+		current += acpi_create_dmar_rmrr(current, 0,
+				sa_get_gsm_base(), sa_get_tolud_base() - 1);
+		current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+		acpi_dmar_rmrr_fixup(tmp, current);
 	}
 
 	/* VTVC0BAR has to be set, enabled, and in 32-bit space */
diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h
index 92e79cc..f414581 100644
--- a/src/soc/intel/broadwell/include/soc/systemagent.h
+++ b/src/soc/intel/broadwell/include/soc/systemagent.h
@@ -137,4 +137,7 @@
 /* System Agent identification */
 u8 systemagent_revision(void);
 
+uintptr_t sa_get_tolud_base(void);
+uintptr_t sa_get_gsm_base(void);
+
 #endif
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index 8013979..e0d8b76 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -36,6 +36,18 @@
 	return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
 }
 
+uintptr_t sa_get_tolud_base(void)
+{
+	/* Bit 0 is lock bit, not part of address */
+	return pci_read_config32(SA_DEV_ROOT, TOLUD) & ~1;
+}
+
+uintptr_t sa_get_gsm_base(void)
+{
+	/* Bit 0 is lock bit, not part of address */
+	return pci_read_config32(SA_DEV_ROOT, BGSM) & ~1;
+}
+
 static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
 			u32 *len)
 {

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d
Gerrit-Change-Number: 30234
Gerrit-PatchSet: 5
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier at gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-MessageType: merged
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