<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30234">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/broadwell: implement RMRR ACPI table<br><br>Modeled after Skylake implementation; uses duplicated<br>intel common SA functions to get RMRR addresses<br><br>Test: build/boot purism/librem13v1, observe IOMMU fully functional<br>with intel_iommu=on kernel parameter<br><br>Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>Reviewed-on: https://review.coreboot.org/c/30234<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/soc/intel/broadwell/acpi.c<br>M src/soc/intel/broadwell/include/soc/systemagent.h<br>M src/soc/intel/broadwell/systemagent.c<br>3 files changed, 24 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c</span><br><span>index 9c6bd9b..42d31c8 100644</span><br><span>--- a/src/soc/intel/broadwell/acpi.c</span><br><span>+++ b/src/soc/intel/broadwell/acpi.c</span><br><span>@@ -590,12 +590,20 @@</span><br><span> /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */</span><br><span> if (igfx_dev && igfx_dev->enabled && gfxvtbar</span><br><span> && gfxvten && !MCHBAR32(GFXVTBAR + 4)) {</span><br><span style="color: hsl(0, 100%, 40%);">- const unsigned long tmp = current;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned long tmp = current;</span><br><span> </span><br><span> current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);</span><br><span> current += acpi_create_dmar_ds_pci(current, 0, 2, 0);</span><br><span> </span><br><span> acpi_dmar_drhd_fixup(tmp, current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Add RMRR entry */</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_rmrr(current, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ sa_get_gsm_base(), sa_get_tolud_base() - 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_ds_pci(current, 0, 2, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_dmar_rmrr_fixup(tmp, current);</span><br><span> }</span><br><span> </span><br><span> /* VTVC0BAR has to be set, enabled, and in 32-bit space */</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h</span><br><span>index 92e79cc..f414581 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/systemagent.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/systemagent.h</span><br><span>@@ -137,4 +137,7 @@</span><br><span> /* System Agent identification */</span><br><span> u8 systemagent_revision(void);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t sa_get_tolud_base(void);</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t sa_get_gsm_base(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c</span><br><span>index 8013979..e0d8b76 100644</span><br><span>--- a/src/soc/intel/broadwell/systemagent.c</span><br><span>+++ b/src/soc/intel/broadwell/systemagent.c</span><br><span>@@ -36,6 +36,18 @@</span><br><span> return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t sa_get_tolud_base(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bit 0 is lock bit, not part of address */</span><br><span style="color: hsl(120, 100%, 40%);">+ return pci_read_config32(SA_DEV_ROOT, TOLUD) & ~1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t sa_get_gsm_base(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bit 0 is lock bit, not part of address */</span><br><span style="color: hsl(120, 100%, 40%);">+ return pci_read_config32(SA_DEV_ROOT, BGSM) & ~1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,</span><br><span> u32 *len)</span><br><span> {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30234">change 30234</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d </div>
<div style="display:none"> Gerrit-Change-Number: 30234 </div>
<div style="display:none"> Gerrit-PatchSet: 5 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Matt DeVillier <matt.devillier@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>