[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Enable DMI/SATA power Optimize

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30212 )

Change subject: mb/google/sarien: Enable DMI/SATA power Optimize
......................................................................

mb/google/sarien: Enable DMI/SATA power Optimize

Turn on power optimizer of PCH side DMI and SATA controller.

BUG=N/A
TEST=Build and boot up into sarien platoform, able to finish 100 cycles
of s0ix.

Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
Change-Id: I41da2b4106d683945cdc296e2a77311176144f43
Reviewed-on: https://review.coreboot.org/c/30212
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park at intel.com>
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
2 files changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved
  Roy Mingi Park: Looks good to me, but someone else must approve



diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index acdb623..a8bb342 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -27,6 +27,8 @@
 	register "speed_shift_enable" = "1"
 	register "s0ix_enable" = "1"
 	register "dptf_enable" = "1"
+	register "dmipwroptimize" = "1"
+	register "satapwroptimize" = "1"
 
 	# Intel Common SoC Config
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Left Type-C Port
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 2800ff5..c24cd02 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -31,6 +31,8 @@
 	register "speed_shift_enable" = "1"
 	register "s0ix_enable" = "1"
 	register "dptf_enable" = "1"
+	register "dmipwroptimize" = "1"
+	register "satapwroptimize" = "1"
 
 	# Intel Common SoC Config
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Left Type-C Port

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I41da2b4106d683945cdc296e2a77311176144f43
Gerrit-Change-Number: 30212
Gerrit-PatchSet: 5
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-MessageType: merged
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