<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30212">View Change</a></p><div style="white-space:pre-wrap">Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved
  Roy Mingi Park: Looks good to me, but someone else must approve

</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/sarien: Enable DMI/SATA power Optimize<br><br>Turn on power optimizer of PCH side DMI and SATA controller.<br><br>BUG=N/A<br>TEST=Build and boot up into sarien platoform, able to finish 100 cycles<br>of s0ix.<br><br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Change-Id: I41da2b4106d683945cdc296e2a77311176144f43<br>Reviewed-on: https://review.coreboot.org/c/30212<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com><br>Reviewed-by: Duncan Laurie <dlaurie@chromium.org><br>---<br>M src/mainboard/google/sarien/variants/arcada/devicetree.cb<br>M src/mainboard/google/sarien/variants/sarien/devicetree.cb<br>2 files changed, 4 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>index acdb623..a8bb342 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>@@ -27,6 +27,8 @@</span><br><span>       register "speed_shift_enable" = "1"</span><br><span>      register "s0ix_enable" = "1"</span><br><span>     register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+      register "dmipwroptimize" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+   register "satapwroptimize" = "1"</span><br><span> </span><br><span>     # Intel Common SoC Config</span><br><span>    register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"      # Left Type-C Port</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>index 2800ff5..c24cd02 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>@@ -31,6 +31,8 @@</span><br><span>      register "speed_shift_enable" = "1"</span><br><span>      register "s0ix_enable" = "1"</span><br><span>     register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+      register "dmipwroptimize" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+   register "satapwroptimize" = "1"</span><br><span> </span><br><span>     # Intel Common SoC Config</span><br><span>    register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"      # Left Type-C Port</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30212">change 30212</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30212"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I41da2b4106d683945cdc296e2a77311176144f43 </div>
<div style="display:none"> Gerrit-Change-Number: 30212 </div>
<div style="display:none"> Gerrit-PatchSet: 5 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>