[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Set Vref Config to 2

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30280


Change subject: mb/google/sarien: Set Vref Config to 2
......................................................................

mb/google/sarien: Set Vref Config to 2

Accoding to desciption in FSP header, Vref Configuration will be set to
2 if VREF_CA to CH_A and VREF_DQ_B to CH_B.

BUG=N/A
TEST=Build and boot up on Arcada platform.

Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
Change-Id: I02e16e141b81d766a6060ca08283f432abd96647
---
M src/mainboard/google/sarien/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/30280/1

diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c
index 7284d55..95af0bc 100644
--- a/src/mainboard/google/sarien/romstage.c
+++ b/src/mainboard/google/sarien/romstage.c
@@ -37,6 +37,9 @@
 
 	/* Disable Early Command Training */
 	.ect = 0,
+
+	/* Base on board design */
+	.vref_ca_config = 2,
 };
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I02e16e141b81d766a6060ca08283f432abd96647
Gerrit-Change-Number: 30280
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-MessageType: newchange
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