<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30280">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/sarien: Set Vref Config to 2<br><br>Accoding to desciption in FSP header, Vref Configuration will be set to<br>2 if VREF_CA to CH_A and VREF_DQ_B to CH_B.<br><br>BUG=N/A<br>TEST=Build and boot up on Arcada platform.<br><br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Change-Id: I02e16e141b81d766a6060ca08283f432abd96647<br>---<br>M src/mainboard/google/sarien/romstage.c<br>1 file changed, 3 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/30280/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c</span><br><span>index 7284d55..95af0bc 100644</span><br><span>--- a/src/mainboard/google/sarien/romstage.c</span><br><span>+++ b/src/mainboard/google/sarien/romstage.c</span><br><span>@@ -37,6 +37,9 @@</span><br><span> </span><br><span>        /* Disable Early Command Training */</span><br><span>         .ect = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   /* Base on board design */</span><br><span style="color: hsl(120, 100%, 40%);">+    .vref_ca_config = 2,</span><br><span> };</span><br><span> </span><br><span> void mainboard_memory_init_params(FSPM_UPD *memupd)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30280">change 30280</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30280"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I02e16e141b81d766a6060ca08283f432abd96647 </div>
<div style="display:none"> Gerrit-Change-Number: 30280 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>