[coreboot-gerrit] Change in ...coreboot[master]: mb/foxconn/g41s-k: Add g41m variant
Arthur Heymans (Code Review)
gerrit at coreboot.org
Sat Dec 15 21:57:47 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30242
Change subject: mb/foxconn/g41s-k: Add g41m variant
......................................................................
mb/foxconn/g41s-k: Add g41m variant
Was tested with the following:
- 2 DIMM slots
- USB
- Ethernet NIC
- automatic fan control
- Libgfxinit (VGA)
- PS2 Keyboard
- SATA
- PEG
What does not work:
- Using the second DIMM slot on a channel
G41 can only handle 2 ranks per channel and on this mainboard 1 rank
per DIMM slot. Supporting this would require too much raminit rework
and is not worth it (at least for me)
Change-Id: I67784038ef929f561b82365f00db70a69c024321
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/foxconn/g41s-k/Kconfig
M src/mainboard/foxconn/g41s-k/Kconfig.name
M src/mainboard/foxconn/g41s-k/Makefile.inc
M src/mainboard/foxconn/g41s-k/acpi/superio.asl
M src/mainboard/foxconn/g41s-k/hda_verb.c
M src/mainboard/foxconn/g41s-k/romstage.c
A src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl
A src/mainboard/foxconn/g41s-k/variants/g41m/data.vbt
A src/mainboard/foxconn/g41s-k/variants/g41m/devicetree.cb
A src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads
R src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl
R src/mainboard/foxconn/g41s-k/variants/g41s-k/data.vbt
R src/mainboard/foxconn/g41s-k/variants/g41s-k/devicetree.cb
R src/mainboard/foxconn/g41s-k/variants/g41s-k/gma-mainboard.ads
14 files changed, 293 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/30242/1
diff --git a/src/mainboard/foxconn/g41s-k/Kconfig b/src/mainboard/foxconn/g41s-k/Kconfig
index 4a534c4..5cea503 100644
--- a/src/mainboard/foxconn/g41s-k/Kconfig
+++ b/src/mainboard/foxconn/g41s-k/Kconfig
@@ -14,7 +14,7 @@
## GNU General Public License for more details.
##
-if BOARD_FOXCONN_G41S_K
+if BOARD_FOXCONN_G41S_K || BOARD_FOXCONN_G41M
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -39,9 +39,18 @@
string
default "foxconn/g41s-k"
+config VARIANT_DIR
+ default "g41s-k" if BOARD_FOXCONN_G41S_K
+ default "g41m" if BOARD_FOXCONN_G41M
+
config MAINBOARD_PART_NUMBER
string
- default "G41S-K"
+ default "G41S-K" if BOARD_FOXCONN_G41S_K
+ default "G41M/G41M-S/G41M-V" if BOARD_FOXCONN_G41M
+
+config DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
config MAX_CPUS
int
diff --git a/src/mainboard/foxconn/g41s-k/Kconfig.name b/src/mainboard/foxconn/g41s-k/Kconfig.name
index 1c618e8..bb33520 100644
--- a/src/mainboard/foxconn/g41s-k/Kconfig.name
+++ b/src/mainboard/foxconn/g41s-k/Kconfig.name
@@ -1,2 +1,4 @@
config BOARD_FOXCONN_G41S_K
bool "G41S-K"
+config BOARD_FOXCONN_G41M
+ bool "G41M/G41M-S/G41M-V"
diff --git a/src/mainboard/foxconn/g41s-k/Makefile.inc b/src/mainboard/foxconn/g41s-k/Makefile.inc
index 0786d6f..6e55214 100644
--- a/src/mainboard/foxconn/g41s-k/Makefile.inc
+++ b/src/mainboard/foxconn/g41s-k/Makefile.inc
@@ -1,4 +1,6 @@
ramstage-y += cstates.c
romstage-y += gpio.c
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/
\ No newline at end of file
diff --git a/src/mainboard/foxconn/g41s-k/acpi/superio.asl b/src/mainboard/foxconn/g41s-k/acpi/superio.asl
index 3811c2f..48180e2 100644
--- a/src/mainboard/foxconn/g41s-k/acpi/superio.asl
+++ b/src/mainboard/foxconn/g41s-k/acpi/superio.asl
@@ -26,10 +26,14 @@
#define SUPERIO_DEV SIO0
#define SUPERIO_PNP_BASE 0x2e
#define IT8720F_SHOW_SP1 1
+#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41K_S)
#define IT8720F_SHOW_SP2 1
+#endif
#define IT8720F_SHOW_EC 1
#define IT8720F_SHOW_KBCK 1
#define IT8720F_SHOW_KBCM 1
#define IT8720F_SHOW_GPIO 1
+#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41K_S)
#define IT8720F_SHOW_CIR 1
+#endif
#include <superio/ite/it8720f/acpi/superio.asl>
diff --git a/src/mainboard/foxconn/g41s-k/hda_verb.c b/src/mainboard/foxconn/g41s-k/hda_verb.c
index 45943b8..cce1ff9 100644
--- a/src/mainboard/foxconn/g41s-k/hda_verb.c
+++ b/src/mainboard/foxconn/g41s-k/hda_verb.c
@@ -17,6 +17,7 @@
#include <device/azalia_device.h>
+#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K)
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0888, /* Vendor ID */
@@ -40,6 +41,31 @@
AZALIA_PIN_CFG(0, 0x1e, 0x01441130),
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
};
+#else /* CONFIG_BOARD_FOXCONN_G41M */
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0888, /* Vendor ID */
+ 0x105b0dc0, /* Subsystem ID */
+ 0x0000000e, /* Number of entries */
+
+ /* Pin Widget Verb Table */
+
+ AZALIA_PIN_CFG(0, 0x11, 0x01441140),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014410),
+ AZALIA_PIN_CFG(0, 0x15, 0x01011412),
+ AZALIA_PIN_CFG(0, 0x16, 0x01016411),
+ AZALIA_PIN_CFG(0, 0x17, 0x01012414),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19c50),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02014c20),
+ AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4007f603),
+ AZALIA_PIN_CFG(0, 0x1e, 0x99430130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+};
+#endif
const u32 pc_beep_verbs[0] = {};
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index 5ea41ea..82b1e76 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -67,7 +67,9 @@
RCBA8(OIC);
RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN |
- FD_ACMOD | FD_ACAUD | FD_PATA | 1;
+ FD_ACMOD | FD_ACAUD | 1;
+ if (IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K))
+ RCBA32(FD) |= FD_PATA;
RCBA32(CG) = 0x00000001;
}
@@ -75,7 +77,7 @@
{
pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |
- COMB_LPC_EN | COMA_LPC_EN);
+ FDD_LPC_EN | COMB_LPC_EN | COMA_LPC_EN);
/* Decode 64 bytes at 0x0a00 to LPC for Super I/O EC and GPIO. */
pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01);
@@ -84,7 +86,11 @@
void mainboard_romstage_entry(unsigned long bist)
{
// ch0 ch1
+#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K)
const u8 spd_addrmap[4] = { 0x50, 0, 0, 0 };
+#else
+ const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
+#endif
u8 boot_path = 0;
u8 s3_resume;
diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..f1f3462
--- /dev/null
+++ b/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur at aheymans.xyz>
+ * Copyright (C) 2017 Samuel Holland <samuel at sholland.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+m *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package() { 0x0001ffff, 0, 0, 0x12},
+ Package() { 0x0001ffff, 1, 0, 0x13},
+ Package() { 0x0001ffff, 2, 0, 0x10},
+ Package() { 0x0001ffff, 3, 0, 0x11},
+
+ Package() { 0x0002ffff, 0, 0, 0x11},
+ Package() { 0x0002ffff, 1, 0, 0x12},
+ Package() { 0x0002ffff, 2, 0, 0x13},
+ Package() { 0x0002ffff, 3, 0, 0x10},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0},
+ })
+}
diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/data.vbt b/src/mainboard/foxconn/g41s-k/variants/g41m/data.vbt
new file mode 100644
index 0000000..fd02a14
--- /dev/null
+++ b/src/mainboard/foxconn/g41s-k/variants/g41m/data.vbt
Binary files differ
diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/devicetree.cb b/src/mainboard/foxconn/g41s-k/variants/g41m/devicetree.cb
new file mode 100644
index 0000000..992026d
--- /dev/null
+++ b/src/mainboard/foxconn/g41s-k/variants/g41m/devicetree.cb
@@ -0,0 +1,164 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+## Copyright (C) 2017 Arthur Heymans <arthur at aheymans.xyz>
+## Copyright (C) 2017 Samuel Holland <samuel at sholland.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/x4x # Northbridge
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x # CPU
+ device lapic 0xACAC off end
+ end
+ end
+ device domain 0 on # PCI domain
+ subsystemid 0x105b 0x0dc0 inherit
+ device pci 0.0 on # Host Bridge
+ subsystemid 0x105b 0x0dda
+ end
+ device pci 1.0 on end # PEG
+ device pci 2.0 on end # Integrated graphics controller
+ device pci 2.1 off end # Integrated graphics controller 2
+ device pci 3.0 off end # ME
+ device pci 3.1 off end # ME
+ chip southbridge/intel/i82801gx # Southbridge
+ register "pirqa_routing" = "0x0a"
+ register "pirqb_routing" = "0x0b"
+ register "pirqc_routing" = "0x0a"
+ register "pirqd_routing" = "0x05"
+ register "pirqe_routing" = "0x0a"
+ register "pirqf_routing" = "0x0b"
+ register "pirqg_routing" = "0x0a"
+ register "pirqh_routing" = "0x03"
+
+ register "gpe0_en" = "0x00000441"
+ register "alt_gp_smi_en" = "0x0000"
+
+ register "ide_enable_primary" = "0x0"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x0" # AHCI does not work
+ register "sata_ports_implemented" = "0x3"
+
+ device pci 1b.0 on end # Audio
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 on # PCIe 2 (NIC)
+ device pci 00.0 on end # PCI 10ec:8168
+ end
+ device pci 1c.2 off end # PCIe 3
+ device pci 1c.3 off end # PCIe 4
+ device pci 1c.4 off end # PCIe 5
+ device pci 1c.5 off end # PCIe 6
+ device pci 1d.0 on end # USB
+ device pci 1d.1 on end # USB
+ device pci 1d.2 on end # USB
+ device pci 1d.3 on end # USB
+ device pci 1d.7 on end # USB
+ device pci 1e.0 on end # PCI bridge
+ device pci 1e.2 off end # AC'97 Audio
+ device pci 1e.3 off end # AC'97 Modem
+ device pci 1f.0 on # ISA bridge
+ chip superio/ite/it8720f # Super I/O
+ register "TMPIN1.mode" = "THERMAL_DIODE"
+ register "TMPIN1.offset" = "0"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_MODE_DISABLED"
+
+ register "ec.vin_mask" = "VIN_ALL"
+
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # System fan
+ register "FAN1.smart.tmpin" = "1"
+ register "FAN1.smart.tmp_off" = "25"
+ register "FAN1.smart.tmp_start" = "30"
+ register "FAN1.smart.tmp_full" = "65"
+ register "FAN1.smart.tmp_delta" = "3"
+ register "FAN1.smart.smoothing" = "1"
+ register "FAN1.smart.pwm_start" = "20"
+ register "FAN1.smart.slope" = "10"
+ register "FAN2.mode" = "FAN_SMART_AUTOMATIC" # CPU fan
+ register "FAN2.smart.tmpin" = "1"
+ register "FAN2.smart.tmp_off" = "25"
+ register "FAN2.smart.tmp_start" = "30"
+ register "FAN2.smart.tmp_full" = "65"
+ register "FAN2.smart.tmp_delta" = "3"
+ register "FAN2.smart.smoothing" = "1"
+ register "FAN2.smart.pwm_start" = "20"
+ register "FAN2.smart.slope" = "10"
+ register "FAN3.mode" = "FAN_MODE_OFF" # Not connected
+
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 0x04
+ irq 0xf0 = 0x00
+ irq 0xf1 = 0x50
+ end
+ device pnp 2e.2 off end # COM2 (IR)
+ device pnp 2e.3 off end # Parallel port
+ device pnp 2e.4 on # Environment controller
+ io 0x60 = 0xa10
+ io 0x62 = 0xa00
+ irq 0x70 = 0x00
+ irq 0xf0 = 0x80
+ irq 0xf1 = 0x00
+ irq 0xf2 = 0x0a
+ irq 0xf3 = 0x00
+ irq 0xf4 = 0x80
+ irq 0xf5 = 0x00
+ irq 0xf6 = 0x00
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x060
+ io 0x62 = 0x064
+ irq 0x70 = 0x01
+ irq 0xf0 = 0x00
+ end
+ device pnp 2e.6 on # Mouse
+ irq 0x70 = 0x0c
+ irq 0xf0 = 0x00
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x000
+ io 0x62 = 0xa20
+ io 0x64 = 0xa30
+ irq 0xf0 = 0x00
+ irq 0xf1 = 0x00
+ irq 0xf2 = 0x00
+ irq 0xf3 = 0x00
+ irq 0xf4 = 0x00
+ irq 0xf5 = 0x00
+ irq 0xf6 = 0x22
+ irq 0xf7 = 0x00
+ irq 0xf8 = 0x00
+ irq 0xf9 = 0x00
+ irq 0xfa = 0x00
+ irq 0xfb = 0x00
+ irq 0xfd = 0x00
+ irq 0xfe = 0x00
+ end
+ device pnp 2e.a off end # CIR
+ end
+ end
+ device pci 1f.1 on end # PATA/IDE
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMbus
+ end
+ end
+end
diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads b/src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads
new file mode 100644
index 0000000..0bf1021
--- /dev/null
+++ b/src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads
@@ -0,0 +1,29 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (Analog,
+ HDMI1,
+ HDMI2,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/foxconn/g41s-k/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl
similarity index 100%
rename from src/mainboard/foxconn/g41s-k/acpi/ich7_pci_irqs.asl
rename to src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl
diff --git a/src/mainboard/foxconn/g41s-k/data.vbt b/src/mainboard/foxconn/g41s-k/variants/g41s-k/data.vbt
similarity index 100%
rename from src/mainboard/foxconn/g41s-k/data.vbt
rename to src/mainboard/foxconn/g41s-k/variants/g41s-k/data.vbt
Binary files differ
diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/variants/g41s-k/devicetree.cb
similarity index 100%
rename from src/mainboard/foxconn/g41s-k/devicetree.cb
rename to src/mainboard/foxconn/g41s-k/variants/g41s-k/devicetree.cb
diff --git a/src/mainboard/foxconn/g41s-k/gma-mainboard.ads b/src/mainboard/foxconn/g41s-k/variants/g41s-k/gma-mainboard.ads
similarity index 100%
rename from src/mainboard/foxconn/g41s-k/gma-mainboard.ads
rename to src/mainboard/foxconn/g41s-k/variants/g41s-k/gma-mainboard.ads
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I67784038ef929f561b82365f00db70a69c024321
Gerrit-Change-Number: 30242
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-MessageType: newchange
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