<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30242">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/foxconn/g41s-k: Add g41m variant<br><br>Was tested with the following:<br>- 2 DIMM slots<br>- USB<br>- Ethernet NIC<br>- automatic fan control<br>- Libgfxinit (VGA)<br>- PS2 Keyboard<br>- SATA<br>- PEG<br><br>What does not work:<br>- Using the second DIMM slot on a channel<br> G41 can only handle 2 ranks per channel and on this mainboard 1 rank<br> per DIMM slot. Supporting this would require too much raminit rework<br> and is not worth it (at least for me)<br><br>Change-Id: I67784038ef929f561b82365f00db70a69c024321<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/foxconn/g41s-k/Kconfig<br>M src/mainboard/foxconn/g41s-k/Kconfig.name<br>M src/mainboard/foxconn/g41s-k/Makefile.inc<br>M src/mainboard/foxconn/g41s-k/acpi/superio.asl<br>M src/mainboard/foxconn/g41s-k/hda_verb.c<br>M src/mainboard/foxconn/g41s-k/romstage.c<br>A src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl<br>A src/mainboard/foxconn/g41s-k/variants/g41m/data.vbt<br>A src/mainboard/foxconn/g41s-k/variants/g41m/devicetree.cb<br>A src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads<br>R src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl<br>R src/mainboard/foxconn/g41s-k/variants/g41s-k/data.vbt<br>R src/mainboard/foxconn/g41s-k/variants/g41s-k/devicetree.cb<br>R src/mainboard/foxconn/g41s-k/variants/g41s-k/gma-mainboard.ads<br>14 files changed, 293 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/30242/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/foxconn/g41s-k/Kconfig b/src/mainboard/foxconn/g41s-k/Kconfig</span><br><span>index 4a534c4..5cea503 100644</span><br><span>--- a/src/mainboard/foxconn/g41s-k/Kconfig</span><br><span>+++ b/src/mainboard/foxconn/g41s-k/Kconfig</span><br><span>@@ -14,7 +14,7 @@</span><br><span> ## GNU General Public License for more details.</span><br><span> ##</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_FOXCONN_G41S_K</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_FOXCONN_G41S_K || BOARD_FOXCONN_G41M</span><br><span> </span><br><span> config BOARD_SPECIFIC_OPTIONS</span><br><span> def_bool y</span><br><span>@@ -39,9 +39,18 @@</span><br><span> string</span><br><span> default "foxconn/g41s-k"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config VARIANT_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ default "g41s-k" if BOARD_FOXCONN_G41S_K</span><br><span style="color: hsl(120, 100%, 40%);">+ default "g41m" if BOARD_FOXCONN_G41M</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span style="color: hsl(0, 100%, 40%);">- default "G41S-K"</span><br><span style="color: hsl(120, 100%, 40%);">+ default "G41S-K" if BOARD_FOXCONN_G41S_K</span><br><span style="color: hsl(120, 100%, 40%);">+ default "G41M/G41M-S/G41M-V" if BOARD_FOXCONN_G41M</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"</span><br><span> </span><br><span> config MAX_CPUS</span><br><span> int</span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/Kconfig.name b/src/mainboard/foxconn/g41s-k/Kconfig.name</span><br><span>index 1c618e8..bb33520 100644</span><br><span>--- a/src/mainboard/foxconn/g41s-k/Kconfig.name</span><br><span>+++ b/src/mainboard/foxconn/g41s-k/Kconfig.name</span><br><span>@@ -1,2 +1,4 @@</span><br><span> config BOARD_FOXCONN_G41S_K</span><br><span> bool "G41S-K"</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_FOXCONN_G41M</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "G41M/G41M-S/G41M-V"</span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/Makefile.inc b/src/mainboard/foxconn/g41s-k/Makefile.inc</span><br><span>index 0786d6f..6e55214 100644</span><br><span>--- a/src/mainboard/foxconn/g41s-k/Makefile.inc</span><br><span>+++ b/src/mainboard/foxconn/g41s-k/Makefile.inc</span><br><span>@@ -1,4 +1,6 @@</span><br><span> ramstage-y += cstates.c</span><br><span> romstage-y += gpio.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/acpi/superio.asl b/src/mainboard/foxconn/g41s-k/acpi/superio.asl</span><br><span>index 3811c2f..48180e2 100644</span><br><span>--- a/src/mainboard/foxconn/g41s-k/acpi/superio.asl</span><br><span>+++ b/src/mainboard/foxconn/g41s-k/acpi/superio.asl</span><br><span>@@ -26,10 +26,14 @@</span><br><span> #define SUPERIO_DEV SIO0</span><br><span> #define SUPERIO_PNP_BASE 0x2e</span><br><span> #define IT8720F_SHOW_SP1 1</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41K_S)</span><br><span> #define IT8720F_SHOW_SP2 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> #define IT8720F_SHOW_EC 1</span><br><span> #define IT8720F_SHOW_KBCK 1</span><br><span> #define IT8720F_SHOW_KBCM 1</span><br><span> #define IT8720F_SHOW_GPIO 1</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41K_S)</span><br><span> #define IT8720F_SHOW_CIR 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> #include <superio/ite/it8720f/acpi/superio.asl></span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/hda_verb.c b/src/mainboard/foxconn/g41s-k/hda_verb.c</span><br><span>index 45943b8..cce1ff9 100644</span><br><span>--- a/src/mainboard/foxconn/g41s-k/hda_verb.c</span><br><span>+++ b/src/mainboard/foxconn/g41s-k/hda_verb.c</span><br><span>@@ -17,6 +17,7 @@</span><br><span> </span><br><span> #include <device/azalia_device.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K)</span><br><span> const u32 cim_verb_data[] = {</span><br><span> /* coreboot specific header */</span><br><span> 0x10ec0888, /* Vendor ID */</span><br><span>@@ -40,6 +41,31 @@</span><br><span> AZALIA_PIN_CFG(0, 0x1e, 0x01441130),</span><br><span> AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),</span><br><span> };</span><br><span style="color: hsl(120, 100%, 40%);">+#else /* CONFIG_BOARD_FOXCONN_G41M */</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* coreboot specific header */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10ec0888, /* Vendor ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x105b0dc0, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000000e, /* Number of entries */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Widget Verb Table */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x11, 0x01441140),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x14, 0x01014410),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x15, 0x01011412),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x16, 0x01016411),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x17, 0x01012414),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x18, 0x01a19c50),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1b, 0x02014c20),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1d, 0x4007f603),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1e, 0x99430130),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> const u32 pc_beep_verbs[0] = {};</span><br><span> </span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c</span><br><span>index 5ea41ea..82b1e76 100644</span><br><span>--- a/src/mainboard/foxconn/g41s-k/romstage.c</span><br><span>+++ b/src/mainboard/foxconn/g41s-k/romstage.c</span><br><span>@@ -67,7 +67,9 @@</span><br><span> RCBA8(OIC);</span><br><span> </span><br><span> RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN |</span><br><span style="color: hsl(0, 100%, 40%);">- FD_ACMOD | FD_ACAUD | FD_PATA | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ FD_ACMOD | FD_ACAUD | 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K))</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(FD) |= FD_PATA;</span><br><span> RCBA32(CG) = 0x00000001;</span><br><span> }</span><br><span> </span><br><span>@@ -75,7 +77,7 @@</span><br><span> {</span><br><span> pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);</span><br><span> pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |</span><br><span style="color: hsl(0, 100%, 40%);">- COMB_LPC_EN | COMA_LPC_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ FDD_LPC_EN | COMB_LPC_EN | COMA_LPC_EN);</span><br><span> </span><br><span> /* Decode 64 bytes at 0x0a00 to LPC for Super I/O EC and GPIO. */</span><br><span> pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01);</span><br><span>@@ -84,7 +86,11 @@</span><br><span> void mainboard_romstage_entry(unsigned long bist)</span><br><span> {</span><br><span> // ch0 ch1</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K)</span><br><span> const u8 spd_addrmap[4] = { 0x50, 0, 0, 0 };</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> u8 boot_path = 0;</span><br><span> u8 s3_resume;</span><br><span> </span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..f1f3462</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/g41s-k/variants/g41m/acpi/ich7_pci_irqs.asl</span><br><span>@@ -0,0 +1,46 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Samuel Holland <samuel@sholland.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+m *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This is board specific information:</span><br><span style="color: hsl(120, 100%, 40%);">+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 0, 0, 0x12},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 1, 0, 0x13},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 2, 0, 0x10},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 3, 0, 0x11},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 0, 0, 0x11},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 1, 0, 0x12},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 2, 0, 0x13},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 3, 0, 0x10},</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+} Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/data.vbt b/src/mainboard/foxconn/g41s-k/variants/g41m/data.vbt</span><br><span>new file mode 100644</span><br><span>index 0000000..fd02a14</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/g41s-k/variants/g41m/data.vbt</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/devicetree.cb b/src/mainboard/foxconn/g41s-k/variants/g41m/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..992026d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/g41s-k/variants/g41m/devicetree.cb</span><br><span>@@ -0,0 +1,164 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2017 Samuel Holland <samuel@sholland.org></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+## (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/x4x # Northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on # APIC cluster</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_LGA775</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_1067x # CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xACAC off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on # PCI domain</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x105b 0x0dc0 inherit</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x105b 0x0dda</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1.0 on end # PEG</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.0 on end # Integrated graphics controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.1 off end # Integrated graphics controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.0 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.1 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/i82801gx # Southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "0x0a"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "0x0a"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "0x05"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "0x0a"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "0x0a"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "0x03"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_en" = "0x00000441"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "alt_gp_smi_en" = "0x0000"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ide_enable_primary" = "0x0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ide_enable_secondary" = "0x0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_ahci" = "0x0" # AHCI does not work</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_ports_implemented" = "0x3"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on end # Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCIe 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on # PCIe 2 (NIC)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # PCI 10ec:8168</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCIe 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCIe 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 off end # PCIe 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCIe 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 off end # AC'97 Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # AC'97 Modem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # ISA bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/ite/it8720f # Super I/O</span><br><span style="color: hsl(120, 100%, 40%);">+ register "TMPIN1.mode" = "THERMAL_DIODE"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "TMPIN1.offset" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "TMPIN2.mode" = "THERMAL_RESISTOR"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "TMPIN3.mode" = "THERMAL_MODE_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ec.vin_mask" = "VIN_ALL"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # System fan</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.tmpin" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.tmp_off" = "25"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.tmp_start" = "30"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.tmp_full" = "65"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.tmp_delta" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.smoothing" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.pwm_start" = "20"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN1.smart.slope" = "10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN2.mode" = "FAN_SMART_AUTOMATIC" # CPU fan</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN2.smart.tmpin" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN2.smart.tmp_off" = "25"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN2.smart.tmp_start" = "30"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN2.smart.tmp_full" = "65"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN2.smart.tmp_delta" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN2.smart.smoothing" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN2.smart.pwm_start" = "20"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN2.smart.slope" = "10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FAN3.mode" = "FAN_MODE_OFF" # Not connected</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 on # Floppy</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f0</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 6</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 on # COM1</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf1 = 0x50</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 off end # COM2 (IR)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 off end # Parallel port</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.4 on # Environment controller</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0xa10</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0xa00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf1 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf2 = 0x0a</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf3 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf4 = 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf5 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf6 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # Keyboard</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x060</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x064</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 on # Mouse</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0x0c</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 on # GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x000</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0xa20</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x64 = 0xa30</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf1 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf2 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf3 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf4 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf5 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf6 = 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf7 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf8 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf9 = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xfa = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xfb = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xfd = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xfe = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a off end # CIR</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # PATA/IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # SMbus</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads b/src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads</span><br><span>new file mode 100644</span><br><span>index 0000000..0bf1021</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/g41s-k/variants/g41m/gma-mainboard.ads</span><br><span>@@ -0,0 +1,29 @@</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+-- it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+-- the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+-- (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+-- but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+-- GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+with HW.GFX.GMA;</span><br><span style="color: hsl(120, 100%, 40%);">+with HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+use HW.GFX.GMA;</span><br><span style="color: hsl(120, 100%, 40%);">+use HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+private package GMA.Mainboard is</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ports : constant Port_List :=</span><br><span style="color: hsl(120, 100%, 40%);">+ (Analog,</span><br><span style="color: hsl(120, 100%, 40%);">+ HDMI1,</span><br><span style="color: hsl(120, 100%, 40%);">+ HDMI2,</span><br><span style="color: hsl(120, 100%, 40%);">+ others => Disabled);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+end GMA.Mainboard;</span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/foxconn/g41s-k/acpi/ich7_pci_irqs.asl</span><br><span>rename to src/mainboard/foxconn/g41s-k/variants/g41s-k/acpi/ich7_pci_irqs.asl</span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/data.vbt b/src/mainboard/foxconn/g41s-k/variants/g41s-k/data.vbt</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/foxconn/g41s-k/data.vbt</span><br><span>rename to src/mainboard/foxconn/g41s-k/variants/g41s-k/data.vbt</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/variants/g41s-k/devicetree.cb</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/foxconn/g41s-k/devicetree.cb</span><br><span>rename to src/mainboard/foxconn/g41s-k/variants/g41s-k/devicetree.cb</span><br><span>diff --git a/src/mainboard/foxconn/g41s-k/gma-mainboard.ads b/src/mainboard/foxconn/g41s-k/variants/g41s-k/gma-mainboard.ads</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/foxconn/g41s-k/gma-mainboard.ads</span><br><span>rename to src/mainboard/foxconn/g41s-k/variants/g41s-k/gma-mainboard.ads</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30242">change 30242</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30242"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I67784038ef929f561b82365f00db70a69c024321 </div>
<div style="display:none"> Gerrit-Change-Number: 30242 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>