[coreboot-gerrit] Change in ...coreboot[master]: [WIP]mb/google/sarien: Enable DMI/SATA power Optimize
Lijian Zhao (Code Review)
gerrit at coreboot.org
Thu Dec 13 18:35:32 CET 2018
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30212
Change subject: [WIP]mb/google/sarien: Enable DMI/SATA power Optimize
......................................................................
[WIP]mb/google/sarien: Enable DMI/SATA power Optimize
Turn on power optimizer for power saving.
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
Change-Id: I41da2b4106d683945cdc296e2a77311176144f43
---
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
A src/mainboard/google/sarien/variants/arcada/devicetree.cb.orig
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
3 files changed, 256 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30212/1
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index ed2c34c..4e99fca 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -27,6 +27,8 @@
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
+ register "dmipwroptimize" = "1"
+ register "satapwroptimize" = "1"
# Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb.orig b/src/mainboard/google/sarien/variants/arcada/devicetree.cb.orig
new file mode 100644
index 0000000..a7f57d2
--- /dev/null
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb.orig
@@ -0,0 +1,252 @@
+chip soc/intel/cannonlake
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "PMC_GPP_A"
+ register "gpe0_dw1" = "PMC_GPP_C"
+ register "gpe0_dw2" = "PMC_GPP_D"
+
+ # EC host command ranges
+ register "gen1_dec" = "0x00040931" # 0x930-0x937
+ register "gen2_dec" = "0x00040941" # 0x940-0x947
+ register "gen3_dec" = "0x000c0951" # 0x950-0x95f
+
+ # FSP configuration
+ register "SaGv" = "3"
+ register "HeciEnabled" = "1"
+ register "SataSalpSupport" = "1"
+<<<<<<< HEAD
+ register "SataMode" = "0"
+=======
+ register "SataMode" = "Sata_AHCI"
+ register "SataPortsEnable[0]" = "0"
+ register "SataPortsEnable[1]" = "1"
+>>>>>>> aef7204a3f... mb/google/sarien: Use meaningful Satamode
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[2]" = "1"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "VmxEnable" = "1"
+
+ register "speed_shift_enable" = "1"
+ register "s0ix_enable" = "1"
+ register "dptf_enable" = "1"
+
+ # Intel Common SoC Config
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port
+ register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port
+ register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port
+ register "usb2_ports[3]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[4]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
+ register "usb3_ports[4]" = "USB3_PORT_EMPTY"
+ register "usb3_ports[5]" = "USB3_PORT_EMPTY"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
+ #| I2C0 | Touchscreen |
+ #| I2C1 | Touchpad |
+ #| I2C4 | H1 TPM |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 216,
+ .fall_time_ns = 28,
+ },
+ .i2c[4] = {
+ .early_init = 1,
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 452,
+ .fall_time_ns = 110,
+ },
+ }"
+
+ # PCIe port 10 for M.2 2230 WLAN
+ register "PcieRpEnable[9]" = "1"
+ register "PcieClkSrcUsage[2]" = "9"
+ register "PcieClkSrcClkReq[2]" = "2"
+
+ # PCIe port 11 for card reader
+ register "PcieRpEnable[10]" = "1"
+ register "PcieClkSrcUsage[1]" = "10"
+ register "PcieClkSrcClkReq[1]" = "1"
+
+ # PCIe port 12 for M.2 3042
+ register "PcieRpEnable[11]" = "1"
+ register "PcieClkSrcUsage[3]" = "11"
+ register "PcieClkSrcClkReq[3]" = "3"
+
+ # PCIe port 13 for M.2 2280 SSD
+ register "PcieRpEnable[12]" = "1"
+ register "PcieClkSrcUsage[4]" = "12"
+ register "PcieClkSrcClkReq[4]" = "4"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 on end # SA Thermal device
+ device pci 12.0 on end # Thermal Subsystem
+ device pci 12.5 off end # UFS SCS
+ device pci 12.6 off end # GSPI #2
+ device pci 13.0 on end # Integrated Sensor Hub
+ device pci 14.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Root Hub""
+ register "type" = "UPC_TYPE_HUB"
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device usb 2.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-A Port""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 2.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-A Port""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 2.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""WWAN""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USH""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.7 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Fingerprint""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.8 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.9 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device usb 3.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-A Port""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 3.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-A Port""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 3.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""WWAN""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 3.3 on end
+ end
+ end
+ end
+ end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ chip drivers/intel/wifi
+ register "wake" = "PME_B0_EN_BIT"
+ device pci 14.3 on end # CNVi wifi
+ end
+ device pci 14.5 off end # SDCard
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""ACPI0C50""
+ register "generic.desc" = ""Touchpad""
+ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
+ register "hid_desc_reg_offset" = "0x20"
+ device i2c 2c on end
+ end
+ end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 on end # SATA
+ device pci 19.0 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)"
+ device i2c 50 on end
+ end
+ end # I2C #4
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 on end # UART #2
+ device pci 1a.0 off end # eMMC
+ device pci 1c.0 off end # PCI Express Port 1 (USB)
+ device pci 1c.1 off end # PCI Express Port 2 (USB)
+ device pci 1c.2 off end # PCI Express Port 3 (USB)
+ device pci 1c.3 off end # PCI Express Port 4 (USB)
+ device pci 1c.4 off end # PCI Express Port 5 (USB)
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9
+ device pci 1d.1 on end # PCI Express Port 10
+ device pci 1d.2 on end # PCI Express Port 11
+ device pci 1d.3 on end # PCI Express Port 12
+ device pci 1d.4 on end # PCI Express Port 13 (x4)
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 on
+ chip ec/google/wilco
+ device pnp 0c09.0 on end
+ end
+ end # LPC/eSPI
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 49200ad..2062ac3 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -31,6 +31,8 @@
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
+ register "dmipwroptimize" = "1"
+ register "satapwroptimize" = "1"
# Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port
--
To view, visit https://review.coreboot.org/c/coreboot/+/30212
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I41da2b4106d683945cdc296e2a77311176144f43
Gerrit-Change-Number: 30212
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-MessageType: newchange
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