<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30212">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]mb/google/sarien: Enable DMI/SATA power Optimize<br><br>Turn on power optimizer for power saving.<br><br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Change-Id: I41da2b4106d683945cdc296e2a77311176144f43<br>---<br>M src/mainboard/google/sarien/variants/arcada/devicetree.cb<br>A src/mainboard/google/sarien/variants/arcada/devicetree.cb.orig<br>M src/mainboard/google/sarien/variants/sarien/devicetree.cb<br>3 files changed, 256 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30212/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>index ed2c34c..4e99fca 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>@@ -27,6 +27,8 @@</span><br><span> register "speed_shift_enable" = "1"</span><br><span> register "s0ix_enable" = "1"</span><br><span> register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dmipwroptimize" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "satapwroptimize" = "1"</span><br><span> </span><br><span> # Intel Common SoC Config</span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port</span><br><span>diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb.orig b/src/mainboard/google/sarien/variants/arcada/devicetree.cb.orig</span><br><span>new file mode 100644</span><br><span>index 0000000..a7f57d2</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb.orig</span><br><span>@@ -0,0 +1,252 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/cannonlake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "PMC_GPP_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "PMC_GPP_C"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "PMC_GPP_D"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command ranges</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00040931" # 0x930-0x937</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x00040941" # 0x940-0x947</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen3_dec" = "0x000c0951" # 0x950-0x95f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "HeciEnabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSalpSupport" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+<<<<<<< HEAD</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataMode" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+=======</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataMode" = "Sata_AHCI"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[0]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+>>>>>>> aef7204a3f... mb/google/sarien: Use meaningful Satamode</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "InternalGfx" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SkipExtGfxScan" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "VmxEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "s0ix_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Intel Common SoC Config</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[3]" = "USB2_PORT_EMPTY"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_EMPTY"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[4]" = "USB3_PORT_EMPTY"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[5]" = "USB3_PORT_EMPTY"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Intel Common SoC Config</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Field | Value |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| I2C0 | Touchscreen |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| I2C1 | Touchpad |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| I2C4 | H1 TPM |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .i2c[0] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .i2c[1] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rise_time_ns = 216,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fall_time_ns = 28,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .i2c[4] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .early_init = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rise_time_ns = 452,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fall_time_ns = 110,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PCIe port 10 for M.2 2230 WLAN</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[9]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[2]" = "9"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[2]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PCIe port 11 for card reader</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[1]" = "10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PCIe port 12 for M.2 3042</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[3]" = "11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[3]" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PCIe port 13 for M.2 2280 SSD</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[12]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcUsage[4]" = "12"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieClkSrcClkReq[4]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 on end # SA Thermal device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.5 off end # UFS SCS</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.6 off end # GSPI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.0 on end # Integrated Sensor Hub</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Root Hub""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_HUB"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 0.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Left Type-C Port""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "group" = "ACPI_PLD_GROUP(1, 1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Left Type-A Port""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "group" = "ACPI_PLD_GROUP(1, 2)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.1 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Right Type-A Port""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "group" = "ACPI_PLD_GROUP(2, 1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.2 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Camera""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_INTERNAL"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.5 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""WWAN""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_INTERNAL"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.6 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USH""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_INTERNAL"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.7 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Fingerprint""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_INTERNAL"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.8 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Bluetooth""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_INTERNAL"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.9 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Left Type-C Port""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "group" = "ACPI_PLD_GROUP(1, 1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Left Type-A Port""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_USB3_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "group" = "ACPI_PLD_GROUP(1, 2)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.1 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Right Type-A Port""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_USB3_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "group" = "ACPI_PLD_GROUP(2, 1)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.2 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""WWAN""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_INTERNAL"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.3 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "PME_B0_EN_BIT"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.3 on end # CNVi wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.5 off end # SDCard</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # I2C #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/hid</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.hid" = ""ACPI0C50""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.desc" = ""Touchpad""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid_desc_reg_offset" = "0x20"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 2c on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 off end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 off end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = ""GOOG0005""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 50 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # I2C #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 off end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 off end # PCI Express Port 1 (USB)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCI Express Port 2 (USB)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCI Express Port 3 (USB)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCI Express Port 4 (USB)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 off end # PCI Express Port 5 (USB)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 on end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 on end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 on end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.4 on end # PCI Express Port 13 (x4)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off end # UART #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 off end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/google/wilco</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c09.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC/eSPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>index 49200ad..2062ac3 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>@@ -31,6 +31,8 @@</span><br><span> register "speed_shift_enable" = "1"</span><br><span> register "s0ix_enable" = "1"</span><br><span> register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dmipwroptimize" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "satapwroptimize" = "1"</span><br><span> </span><br><span> # Intel Common SoC Config</span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30212">change 30212</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30212"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I41da2b4106d683945cdc296e2a77311176144f43 </div>
<div style="display:none"> Gerrit-Change-Number: 30212 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>