[coreboot-gerrit] Change in ...coreboot[master]: mainboard/lenovo: Add ThinkPad T431s
Bill XIE (Code Review)
gerrit at coreboot.org
Mon Dec 3 13:18:55 CET 2018
Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30021
Change subject: mainboard/lenovo: Add ThinkPad T431s
......................................................................
mainboard/lenovo: Add ThinkPad T431s
The code is based on autoport and that for T430s
Tested:
- CPU i5-3337U
- Slotted DIMM 2GiB
- Soldered RAM 4GiB from samsung (There may be more models here)
- Camera
- pci-e and usb2 on M.2 slot with A key for wlan
- sata and usb2 (no superspeed components) on M.2 slot with B key for wwan
- On board SDHCI connected to pci-e
- USB3 ports
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- TPM1 on LPC
- EHCI debug on SSP2 (USB3 port on the left)
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
Linux payload (Heads), Seabios may also work.
Not tested:
- Fingerprint reader on USB2 (not present on mine)
- Keyboard backlight (not present on mine)
- "sticky_fn" flag in nvram
Not implemented yet:
- Fn locking in nvram (may not be identical to "sticky_fn")
- Detecting the model of Soldered RAM at runtime, and loading the
corresponding SPD datum (3 observed) from CBFS (the mechanism may be
similar to that on x1_carbon_gen1 and s230u, but I do not know how
to find gpio ports for that, and SPD data stored in vendor firmware.)
Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a
Signed-off-by: Bill XIE <persmule at gmail.com>
---
M Documentation/mainboard/index.md
A Documentation/mainboard/lenovo/t431s.md
A Documentation/mainboard/lenovo/t431s_bc_removed.jpg
A Documentation/mainboard/lenovo/t431s_flash_chip.jpg
A Documentation/mainboard/lenovo/t431s_programming.jpg
A src/mainboard/lenovo/t431s/Kconfig
A src/mainboard/lenovo/t431s/Kconfig.name
A src/mainboard/lenovo/t431s/Makefile.inc
A src/mainboard/lenovo/t431s/acpi/ec.asl
A src/mainboard/lenovo/t431s/acpi/platform.asl
A src/mainboard/lenovo/t431s/acpi/superio.asl
A src/mainboard/lenovo/t431s/acpi_tables.c
A src/mainboard/lenovo/t431s/board_info.txt
A src/mainboard/lenovo/t431s/cmos.default
A src/mainboard/lenovo/t431s/cmos.layout
A src/mainboard/lenovo/t431s/data.vbt
A src/mainboard/lenovo/t431s/devicetree.cb
A src/mainboard/lenovo/t431s/dsdt.asl
A src/mainboard/lenovo/t431s/gma-mainboard.ads
A src/mainboard/lenovo/t431s/gpio.c
A src/mainboard/lenovo/t431s/hda_verb.c
A src/mainboard/lenovo/t431s/mainboard.c
A src/mainboard/lenovo/t431s/romstage.c
A src/mainboard/lenovo/t431s/spd/Makefile.inc
A src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex
A src/mainboard/lenovo/t431s/thermal.h
26 files changed, 1,133 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30021/1
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 128f0c1..356f203 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -60,6 +60,7 @@
- [T530](lenovo/w530.md)
- [W530](lenovo/w530.md)
- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)
+- [T431s](lenovo/t431s.md)
## SiFive
diff --git a/Documentation/mainboard/lenovo/t431s.md b/Documentation/mainboard/lenovo/t431s.md
new file mode 100644
index 0000000..9a8a4b9
--- /dev/null
+++ b/Documentation/mainboard/lenovo/t431s.md
@@ -0,0 +1,33 @@
+# Lenovo T431s
+
+## disassembly instructions
+
+You must remove the following parts before flipping the mainboard
+off the main frame:
+
+
+
+* Base cover
+* Hard disk drive
+* Battery pack
+* Keyboard
+
+Its [Hardware Maintenance Manual](https://thinkpads.com/support/hmm/hmm_pdf/t431s_hmm_en_0c10894_02.pdf) could be used as a guidance of disassembly.
+
+
+
+The WSON-8 flash chip (surrounded with red circle in the photo above)
+sits on the opposite side of the mainboard, under a piece of insulating
+stick. If solders between the chip and soldering pads fortunately
+overflows beside the chip as tiny tin balls attached to soldering pads,
+it will be possible to use a pomona 5250 clip to hold the chip, with
+its metal tips just attached to tin balls, thus connecting the chip to
+the programmer.
+
+
+
+```eval_rst
+:doc:`../../flash_tutorial/ext_power`
+```
+
+[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md
diff --git a/Documentation/mainboard/lenovo/t431s_bc_removed.jpg b/Documentation/mainboard/lenovo/t431s_bc_removed.jpg
new file mode 100644
index 0000000..4f8ddd6
--- /dev/null
+++ b/Documentation/mainboard/lenovo/t431s_bc_removed.jpg
Binary files differ
diff --git a/Documentation/mainboard/lenovo/t431s_flash_chip.jpg b/Documentation/mainboard/lenovo/t431s_flash_chip.jpg
new file mode 100644
index 0000000..48c861e
--- /dev/null
+++ b/Documentation/mainboard/lenovo/t431s_flash_chip.jpg
Binary files differ
diff --git a/Documentation/mainboard/lenovo/t431s_programming.jpg b/Documentation/mainboard/lenovo/t431s_programming.jpg
new file mode 100644
index 0000000..c49562a
--- /dev/null
+++ b/Documentation/mainboard/lenovo/t431s_programming.jpg
Binary files differ
diff --git a/src/mainboard/lenovo/t431s/Kconfig b/src/mainboard/lenovo/t431s/Kconfig
new file mode 100644
index 0000000..b6e06c6
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/Kconfig
@@ -0,0 +1,65 @@
+if BOARD_LENOVO_T431S
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SYSTEM_TYPE_LAPTOP
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select USE_NATIVE_RAMINIT
+ select SOUTHBRIDGE_INTEL_C216
+ select EC_LENOVO_PMH7
+ select EC_LENOVO_H8
+ select NO_UART_ON_SUPERIO
+ select BOARD_ROMSIZE_KB_16384
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select HAVE_ACPI_RESUME
+ select INTEL_INT15
+ select SANDYBRIDGE_IVYBRIDGE_LVDS
+ select ENABLE_VMX
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM1
+ select MAINBOARD_HAS_LIBGFXINIT
+ select INTEL_GMA_HAVE_VBT
+
+ # Workaround for EC/KBC IRQ1.
+ select SERIRQ_CONTINUOUS_MODE
+
+config MAINBOARD_DIR
+ string
+ default lenovo/t431s
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ThinkPad T431s"
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 2
+
+config DRAM_RESET_GATE_GPIO
+ int
+ default 10
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x17aa
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x2208
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+endif # BOARD_LENOVO_T431S
diff --git a/src/mainboard/lenovo/t431s/Kconfig.name b/src/mainboard/lenovo/t431s/Kconfig.name
new file mode 100644
index 0000000..4a0fdba
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_LENOVO_T431S
+ bool "ThinkPad T431s"
diff --git a/src/mainboard/lenovo/t431s/Makefile.inc b/src/mainboard/lenovo/t431s/Makefile.inc
new file mode 100644
index 0000000..a312a0f
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/Makefile.inc
@@ -0,0 +1,19 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+subdirs-y += spd
\ No newline at end of file
diff --git a/src/mainboard/lenovo/t431s/acpi/ec.asl b/src/mainboard/lenovo/t431s/acpi/ec.asl
new file mode 100644
index 0000000..d631f12
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/acpi/ec.asl
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <ec/lenovo/h8/acpi/ec.asl>
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+}
diff --git a/src/mainboard/lenovo/t431s/acpi/platform.asl b/src/mainboard/lenovo/t431s/acpi/platform.asl
new file mode 100644
index 0000000..e4c8a24
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/acpi/platform.asl
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ \_SB.PCI0.LPCB.EC.MUTE(1)
+ \_SB.PCI0.LPCB.EC.USBP(0)
+ \_SB.PCI0.LPCB.EC.RADI(0)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ /* ME may not be up yet. */
+ Store (0, \_TZ.MEB1)
+ Store (0, \_TZ.MEB2)
+
+ /* Wake the HKEY to init BT/WWAN */
+ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)
+
+ /* Not implemented. */
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/lenovo/t431s/acpi/superio.asl b/src/mainboard/lenovo/t431s/acpi/superio.asl
new file mode 100644
index 0000000..f2b35ba
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/lenovo/t431s/acpi_tables.c b/src/mainboard/lenovo/t431s/acpi_tables.c
new file mode 100644
index 0000000..279674d
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/acpi_tables.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ acpi_update_thermal_table(gnvs);
+}
diff --git a/src/mainboard/lenovo/t431s/board_info.txt b/src/mainboard/lenovo/t431s/board_info.txt
new file mode 100644
index 0000000..11f5e87
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8 / WSON-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2013
diff --git a/src/mainboard/lenovo/t431s/cmos.default b/src/mainboard/lenovo/t431s/cmos.default
new file mode 100644
index 0000000..979f132
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/cmos.default
@@ -0,0 +1,16 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+volume=0x3
+first_battery=Primary
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+touchpad=Enable
+sata_mode=AHCI
+fn_ctrl_swap=Disable
+sticky_fn=Disable
+trackpoint=Enable
+backlight=Both
+usb_always_on=Disable
diff --git a/src/mainboard/lenovo/t431s/cmos.layout b/src/mainboard/lenovo/t431s/cmos.layout
new file mode 100644
index 0000000..62a6ad45
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/cmos.layout
@@ -0,0 +1,136 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: EC
+411 1 e 8 first_battery
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 touchpad
+415 1 e 1 wlan
+416 1 e 1 trackpoint
+417 1 e 1 fn_ctrl_swap
+418 1 e 1 sticky_fn
+419 2 e 12 usb_always_on
+421 1 e 9 sata_mode
+422 2 e 10 backlight
+
+# coreboot config options: cpu
+#424 8 r 0 unused
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+#435 1 e 1 enable_dual_graphics
+#436 4 r 0 unused
+440 8 h 0 volume
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+8 0 Secondary
+8 1 Primary
+9 0 AHCI
+9 1 Compatible
+10 0 Both
+10 1 Keyboard only
+10 2 Thinklight only
+10 3 None
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+12 0 Disable
+12 1 AC and battery
+12 2 AC only
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/lenovo/t431s/data.vbt b/src/mainboard/lenovo/t431s/data.vbt
new file mode 100644
index 0000000..7593154
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/data.vbt
Binary files differ
diff --git a/src/mainboard/lenovo/t431s/devicetree.cb b/src/mainboard/lenovo/t431s/devicetree.cb
new file mode 100644
index 0000000..a4286e6
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/devicetree.cb
@@ -0,0 +1,193 @@
+chip northbridge/intel/sandybridge
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+
+ # Enable DisplayPort Hotplug with 6ms pulse
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+
+ # Enable Panel as eDP and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP
+ register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
+ register "gpu_panel_power_up_delay" = "2000" # T1+T2: 10ms
+ register "gpu_panel_power_down_delay" = "500" # T5+T6: 10ms
+ register "gpu_panel_power_backlight_on_delay" = "1" # T3: 210ms
+ register "gpu_panel_power_backlight_off_delay" = "1" # T4: 210ms
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gpu_cpu_backlight" = "0x03d2"
+ register "gpu_pch_backlight" = "0x11551155"
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ register "pci_mmio_size" = "2048"
+
+ device domain 0 on
+ device pci 00.0 on
+ subsystemid 0x17aa 0x2208
+ end # host bridge
+ device pci 01.0 off end # PCIe Bridge for discrete graphics
+ device pci 02.0 on
+ subsystemid 0x17aa 0x2208
+ end # Integrated Graphics Controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "gpi1_routing" = "2"
+ register "gpi13_routing" = "2"
+
+ # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock)
+ register "sata_port_map" = "0x17"
+ # Set max SATA speed to 6.0 Gb/s
+ register "sata_interface_speed_support" = "0x3"
+
+ register "gen1_dec" = "0x7c1601"
+ register "gen2_dec" = "0x0c15e1"
+ register "gen4_dec" = "0x0c06a1"
+
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+
+ # Wire port 4 (wwan usb) to ehci for it lacks superspeed components
+ register "xhci_switchable_ports" = "0x7"
+ register "superspeed_capable_ports" = "0xf"
+ register "xhci_overcurrent_mapping" = "0x4000201"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+ register "c2_latency" = "101" # c2 not supported
+ register "p_cnt_throttling_supported" = "1"
+ register "docking_supported" = "1"
+
+ register "spi_uvscc" = "0x2005"
+ register "spi_lvscc" = "0x2005"
+
+ device pci 14.0 on
+ subsystemid 0x17aa 0x2208
+ end # USB 3.0 Controller
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on
+ subsystemid 0x17aa 0x21f3
+ end # Intel Gigabit Ethernet
+ device pci 1a.0 on
+ subsystemid 0x17aa 0x2208
+ end # USB Enhanced Host Controller #2
+ device pci 1b.0 on
+ subsystemid 0x17aa 0x2208
+ end # High Definition Audio Controller
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x17aa 0x2208
+ chip drivers/ricoh/rce822 # Ricoh cardreader
+ register "disable_mask" = "0x87"
+ register "sdwppol" = "0"
+ device pci 00.0 on # Ricoh SD card reader
+ subsystemid 0x17aa 0x2208
+ end
+ end
+ end
+ device pci 1c.1 on
+ subsystemid 0x17aa 0x2208
+ end # PCIe Port #2 Integrated Wireless LAN
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on
+ subsystemid 0x17aa 0x2208
+ end # USB Enhanced Host Controller #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ subsystemid 0x17aa 0x2208
+ chip ec/lenovo/pmh7
+ device pnp ff.1 on # dummy
+ end
+ register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
+ end
+
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+
+ chip ec/lenovo/h8
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+
+ register "config0" = "0xa6"
+ register "config1" = "0x09"
+ register "config2" = "0xa0"
+ register "config3" = "0xc0"
+
+ register "has_keyboard_backlight" = "1"
+
+ register "beepmask0" = "0x00"
+ register "beepmask1" = "0x86"
+ register "has_power_management_beeps" = "0"
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xd0"
+ register "event5_enable" = "0x3c"
+ register "event6_enable" = "0x00"
+ register "event7_enable" = "0x01"
+ register "event8_enable" = "0x7b"
+ register "event9_enable" = "0xff"
+ register "eventa_enable" = "0x00"
+ register "eventb_enable" = "0x00"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+ register "evente_enable" = "0x1d"
+
+ # T431s only has BT on wlan card
+ register "has_bdc_detection" = "0"
+ end
+ end # LPC Controller
+ device pci 1f.2 on
+ subsystemid 0x17aa 0x2208
+ end # 6 port SATA AHCI Controller
+ device pci 1f.3 on
+ subsystemid 0x17aa 0x2208
+ # eeprom, 8 virtual devices, same chip
+ chip drivers/i2c/at24rf08c
+ device i2c 54 on end
+ device i2c 55 on end
+ device i2c 56 on end
+ device i2c 57 on end
+ device i2c 5c on end
+ device i2c 5d on end
+ device i2c 5e on end
+ device i2c 5f on end
+ end
+ end # SMBus Controller
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/t431s/dsdt.asl b/src/mainboard/lenovo/t431s/dsdt.asl
new file mode 100644
index 0000000..1cb4add
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/dsdt.asl
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define THINKPAD_EC_GPE 17
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+#define EC_LENOVO_H8_ME_WORKAROUND 1
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/lenovo/t431s/gma-mainboard.ads b/src/mainboard/lenovo/t431s/gma-mainboard.ads
new file mode 100644
index 0000000..d635d88
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- Copyright (C) 2017 Bill XIE persmule at gmail.com
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/t431s/gpio.c b/src/mainboard/lenovo/t431s/gpio.c
new file mode 100644
index 0000000..5e0684c
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/gpio.c
@@ -0,0 +1,206 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NATIVE,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_NATIVE,
+ .gpio7 = GPIO_MODE_NATIVE,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_NATIVE,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_NATIVE,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_OUTPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_OUTPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio3 = GPIO_LEVEL_HIGH,
+ .gpio5 = GPIO_LEVEL_LOW,
+ .gpio10 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_NATIVE,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_GPIO,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_OUTPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio43 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_GPIO,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_NATIVE,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT,
+ .gpio65 = GPIO_DIR_INPUT,
+ .gpio66 = GPIO_DIR_INPUT,
+ .gpio67 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/lenovo/t431s/hda_verb.c b/src/mainboard/lenovo/t431s/hda_verb.c
new file mode 100644
index 0000000..179fba0
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/hda_verb.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0269, /* Codec Vendor / Device ID: Realtek */
+ 0x17aa2208, /* Subsystem ID */
+
+ 0x0000000b, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x17aa2208),
+
+ /* NID 0x12. */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140),
+
+ /* NID 0x14. */
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+
+ /* NID 0x15. */
+ AZALIA_PIN_CFG(0x0, 0x15, 0x03211020),
+
+ /* NID 0x17. */
+ AZALIA_PIN_CFG(0x0, 0x17, 0x40008000),
+
+ /* NID 0x18. */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11030),
+
+ /* NID 0x19. */
+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
+
+ /* NID 0x1a. */
+ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
+
+ /* NID 0x1b. */
+ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
+
+ /* NID 0x1d. */
+ AZALIA_PIN_CFG(0x0, 0x1d, 0x40f38205),
+
+ /* NID 0x1e. */
+ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+
+ 0x00000004, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ /* NID 0x05. */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+ /* NID 0x06. */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
+
+ /* NID 0x07. */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/t431s/mainboard.c b/src/mainboard/lenovo/t431s/mainboard.c
new file mode 100644
index 0000000..6c85aba
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/mainboard.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 Google Inc.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <ec/lenovo/h8/h8.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+void h8_mainboard_init_dock(void)
+{
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lenovo/t431s/romstage.c b/src/mainboard/lenovo/t431s/romstage.c
new file mode 100644
index 0000000..c87e218
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/romstage.c
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <option.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
+#include <cbfs.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/lenovo/pmh7/pmh7.h>
+
+void pch_enable_lpc(void)
+{
+ /* EC Decode Range Port60/64, Port62/66 */
+ /* Enable EC, PS/2 Keyboard/Mouse */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 }, /* SSP1: right */
+ { 1, 0, 1 }, /* SSP2: left, EHCI Debug */
+ { 1, 1, 3 }, /* SSP3: dock usb3 */
+ { 1, 1, -1 }, /* B0P4: wwan usb */
+ { 1, 1, 2 }, /* B0P5: dock usb2 */
+ { 0, 0, -1 }, /* B0P6 */
+ { 0, 0, -1 }, /* B0P7 */
+ { 1, 2, -1 }, /* B0P8: unknown */
+ { 1, 0, -1 }, /* B1P1: smart card reader */
+ { 0, 2, 5 }, /* B1P2 */
+ { 1, 1, -1 }, /* B1P3: fingerprint reader */
+ { 0, 0, -1 }, /* B1P4 */
+ { 1, 1, -1 }, /* B1P5: wlan usb */
+ { 1, 1, -1 }, /* B1P6: Camera */
+};
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only) {
+ /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */
+ size_t spd_file_len = 0;
+ void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_file_len);
+
+ if (!spd_file || spd_file_len < sizeof(spd_raw_data))
+ die("SPD data for C1S0 not found.");
+
+ memcpy(&spd[0], spd_file, spd_file_len);
+ read_spd(&spd[2], 0x51, id_only);
+}
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
diff --git a/src/mainboard/lenovo/t431s/spd/Makefile.inc b/src/mainboard/lenovo/t431s/spd/Makefile.inc
new file mode 100644
index 0000000..17bb8fa
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/spd/Makefile.inc
@@ -0,0 +1,31 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Alexander Couzens <lynxis at fe80.eu>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES = samsung_4gb # 0b0010 4GiB
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
\ No newline at end of file
diff --git a/src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex b/src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex
new file mode 100644
index 0000000..252ff3f
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex
@@ -0,0 +1,16 @@
+92 11 0b 03 04 00 00 01 03 52 01 08 0a 00 80 00
+6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 b6 3b
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
\ No newline at end of file
diff --git a/src/mainboard/lenovo/t431s/thermal.h b/src/mainboard/lenovo/t431s/thermal.h
new file mode 100644
index 0000000..1d55584
--- /dev/null
+++ b/src/mainboard/lenovo/t431s/thermal.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef T430S_THERMAL_H
+#define T430S_THERMAL_H
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 90
+
+#endif /* T430S_THERMAL_H */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a
Gerrit-Change-Number: 30021
Gerrit-PatchSet: 1
Gerrit-Owner: Bill XIE <persmule at gmail.com>
Gerrit-MessageType: newchange
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