<p>Bill XIE has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30021">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/lenovo: Add ThinkPad T431s<br><br>The code is based on autoport and that for T430s<br><br>Tested:<br>- CPU i5-3337U<br>- Slotted DIMM 2GiB<br>- Soldered RAM 4GiB from samsung (There may be more models here)<br>- Camera<br>- pci-e and usb2 on M.2 slot with A key for wlan<br>- sata and usb2 (no superspeed components) on M.2 slot with B key for wwan<br>- On board SDHCI connected to pci-e<br>- USB3 ports<br>- NVRAM options for North and South bridges<br>- Sound<br>- Thinkpad EC<br>- S3<br>- TPM1 on LPC<br>- EHCI debug on SSP2 (USB3 port on the left)<br>- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from<br> Linux payload (Heads), Seabios may also work.<br><br>Not tested:<br>- Fingerprint reader on USB2 (not present on mine)<br>- Keyboard backlight (not present on mine)<br>- "sticky_fn" flag in nvram<br><br>Not implemented yet:<br>- Fn locking in nvram (may not be identical to "sticky_fn")<br>- Detecting the model of Soldered RAM at runtime, and loading the<br> corresponding SPD datum (3 observed) from CBFS (the mechanism may be<br> similar to that on x1_carbon_gen1 and s230u, but I do not know how<br> to find gpio ports for that, and SPD data stored in vendor firmware.)<br><br>Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a<br>Signed-off-by: Bill XIE <persmule@gmail.com><br>---<br>M Documentation/mainboard/index.md<br>A Documentation/mainboard/lenovo/t431s.md<br>A Documentation/mainboard/lenovo/t431s_bc_removed.jpg<br>A Documentation/mainboard/lenovo/t431s_flash_chip.jpg<br>A Documentation/mainboard/lenovo/t431s_programming.jpg<br>A src/mainboard/lenovo/t431s/Kconfig<br>A src/mainboard/lenovo/t431s/Kconfig.name<br>A src/mainboard/lenovo/t431s/Makefile.inc<br>A src/mainboard/lenovo/t431s/acpi/ec.asl<br>A src/mainboard/lenovo/t431s/acpi/platform.asl<br>A src/mainboard/lenovo/t431s/acpi/superio.asl<br>A src/mainboard/lenovo/t431s/acpi_tables.c<br>A src/mainboard/lenovo/t431s/board_info.txt<br>A src/mainboard/lenovo/t431s/cmos.default<br>A src/mainboard/lenovo/t431s/cmos.layout<br>A src/mainboard/lenovo/t431s/data.vbt<br>A src/mainboard/lenovo/t431s/devicetree.cb<br>A src/mainboard/lenovo/t431s/dsdt.asl<br>A src/mainboard/lenovo/t431s/gma-mainboard.ads<br>A src/mainboard/lenovo/t431s/gpio.c<br>A src/mainboard/lenovo/t431s/hda_verb.c<br>A src/mainboard/lenovo/t431s/mainboard.c<br>A src/mainboard/lenovo/t431s/romstage.c<br>A src/mainboard/lenovo/t431s/spd/Makefile.inc<br>A src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex<br>A src/mainboard/lenovo/t431s/thermal.h<br>26 files changed, 1,133 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30021/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md</span><br><span>index 128f0c1..356f203 100644</span><br><span>--- a/Documentation/mainboard/index.md</span><br><span>+++ b/Documentation/mainboard/index.md</span><br><span>@@ -60,6 +60,7 @@</span><br><span> - [T530](lenovo/w530.md)</span><br><span> - [W530](lenovo/w530.md)</span><br><span> - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)</span><br><span style="color: hsl(120, 100%, 40%);">+- [T431s](lenovo/t431s.md)</span><br><span> </span><br><span> ## SiFive</span><br><span> </span><br><span>diff --git a/Documentation/mainboard/lenovo/t431s.md b/Documentation/mainboard/lenovo/t431s.md</span><br><span>new file mode 100644</span><br><span>index 0000000..9a8a4b9</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/lenovo/t431s.md</span><br><span>@@ -0,0 +1,33 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# Lenovo T431s</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## disassembly instructions</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+You must remove the following parts before flipping the mainboard</span><br><span style="color: hsl(120, 100%, 40%);">+off the main frame: </span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+![t431s_bc_removed](t431s_bc_removed.jpg)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Base cover</span><br><span style="color: hsl(120, 100%, 40%);">+* Hard disk drive</span><br><span style="color: hsl(120, 100%, 40%);">+* Battery pack</span><br><span style="color: hsl(120, 100%, 40%);">+* Keyboard</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Its [Hardware Maintenance Manual](https://thinkpads.com/support/hmm/hmm_pdf/t431s_hmm_en_0c10894_02.pdf) could be used as a guidance of disassembly.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+![t431s_flash_chip](t431s_flash_chip.jpg)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The WSON-8 flash chip (surrounded with red circle in the photo above)</span><br><span style="color: hsl(120, 100%, 40%);">+sits on the opposite side of the mainboard, under a piece of insulating</span><br><span style="color: hsl(120, 100%, 40%);">+stick. If solders between the chip and soldering pads fortunately</span><br><span style="color: hsl(120, 100%, 40%);">+overflows beside the chip as tiny tin balls attached to soldering pads,</span><br><span style="color: hsl(120, 100%, 40%);">+it will be possible to use a pomona 5250 clip to hold the chip, with</span><br><span style="color: hsl(120, 100%, 40%);">+its metal tips just attached to tin balls, thus connecting the chip to</span><br><span style="color: hsl(120, 100%, 40%);">+the programmer.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+![t431s_programming](t431s_programming.jpg)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">+:doc:`../../flash_tutorial/ext_power`</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md</span><br><span>diff --git a/Documentation/mainboard/lenovo/t431s_bc_removed.jpg b/Documentation/mainboard/lenovo/t431s_bc_removed.jpg</span><br><span>new file mode 100644</span><br><span>index 0000000..4f8ddd6</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/lenovo/t431s_bc_removed.jpg</span><br><span>Binary files differ</span><br><span>diff --git a/Documentation/mainboard/lenovo/t431s_flash_chip.jpg b/Documentation/mainboard/lenovo/t431s_flash_chip.jpg</span><br><span>new file mode 100644</span><br><span>index 0000000..48c861e</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/lenovo/t431s_flash_chip.jpg</span><br><span>Binary files differ</span><br><span>diff --git a/Documentation/mainboard/lenovo/t431s_programming.jpg b/Documentation/mainboard/lenovo/t431s_programming.jpg</span><br><span>new file mode 100644</span><br><span>index 0000000..c49562a</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/lenovo/t431s_programming.jpg</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/lenovo/t431s/Kconfig b/src/mainboard/lenovo/t431s/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..b6e06c6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/Kconfig</span><br><span>@@ -0,0 +1,65 @@</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_LENOVO_T431S</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select SYSTEM_TYPE_LAPTOP</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_INTEL_SOCKET_RPGA989</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_INTEL_IVYBRIDGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select USE_NATIVE_RAMINIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_C216</span><br><span style="color: hsl(120, 100%, 40%);">+ select EC_LENOVO_PMH7</span><br><span style="color: hsl(120, 100%, 40%);">+ select EC_LENOVO_H8</span><br><span style="color: hsl(120, 100%, 40%);">+ select NO_UART_ON_SUPERIO</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_16384</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_INT15</span><br><span style="color: hsl(120, 100%, 40%);">+ select SANDYBRIDGE_IVYBRIDGE_LVDS</span><br><span style="color: hsl(120, 100%, 40%);">+ select ENABLE_VMX</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_LPC_TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_TPM1</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_LIBGFXINIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_GMA_HAVE_VBT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Workaround for EC/KBC IRQ1.</span><br><span style="color: hsl(120, 100%, 40%);">+ select SERIRQ_CONTINUOUS_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default lenovo/t431s</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "ThinkPad T431s"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config USBDEBUG_HCD_INDEX</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DRAM_RESET_GATE_GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VGA_BIOS_FILE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "pci8086,0166.rom"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x17aa</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config ONBOARD_VGA_IS_PRIMARY</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_LENOVO_T431S</span><br><span>diff --git a/src/mainboard/lenovo/t431s/Kconfig.name b/src/mainboard/lenovo/t431s/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..4a0fdba</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_LENOVO_T431S</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "ThinkPad T431s"</span><br><span>diff --git a/src/mainboard/lenovo/t431s/Makefile.inc b/src/mainboard/lenovo/t431s/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..a312a0f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/Makefile.inc</span><br><span>@@ -0,0 +1,19 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += spd</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/lenovo/t431s/acpi/ec.asl b/src/mainboard/lenovo/t431s/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..d631f12</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/acpi/ec.asl</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/lenovo/h8/acpi/ec.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Scope(\_SB.PCI0.LPCB.EC)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/lenovo/t431s/acpi/platform.asl b/src/mainboard/lenovo/t431s/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e4c8a24</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/acpi/platform.asl</span><br><span>@@ -0,0 +1,40 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The _PTS method (Prepare To Sleep) is called before the OS is</span><br><span style="color: hsl(120, 100%, 40%);">+ * entering a sleep state. The sleep state number is passed in Arg0</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PTS,1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.PCI0.LPCB.EC.MUTE(1)</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.PCI0.LPCB.EC.USBP(0)</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.PCI0.LPCB.EC.RADI(0)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The _WAK method is called on system wakeup */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_WAK,1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME may not be up yet. */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, \_TZ.MEB1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, \_TZ.MEB2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Wake the HKEY to init BT/WWAN */</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Not implemented. */</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(Package(){0,0})</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/lenovo/t431s/acpi/superio.asl b/src/mainboard/lenovo/t431s/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..f2b35ba</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/acpi/superio.asl</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/pc80/pc/ps2_controller.asl></span><br><span>diff --git a/src/mainboard/lenovo/t431s/acpi_tables.c b/src/mainboard/lenovo/t431s/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..279674d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/acpi_tables.c</span><br><span>@@ -0,0 +1,39 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "thermal.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void acpi_update_thermal_table(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->tcrt = CRITICAL_TEMPERATURE;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->tpsv = PASSIVE_TEMPERATURE;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable USB ports in S3 by default */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s3u0 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s3u1 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable USB ports in S5 by default */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u0 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u1 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // the lid is open by default.</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->lids = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_update_thermal_table(gnvs);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/lenovo/t431s/board_info.txt b/src/mainboard/lenovo/t431s/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..11f5e87</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/board_info.txt</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: laptop</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: SOIC-8 / WSON-8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: n</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2013</span><br><span>diff --git a/src/mainboard/lenovo/t431s/cmos.default b/src/mainboard/lenovo/t431s/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..979f132</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/cmos.default</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option=Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level=Debug</span><br><span style="color: hsl(120, 100%, 40%);">+power_on_after_fail=Disable</span><br><span style="color: hsl(120, 100%, 40%);">+nmi=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+volume=0x3</span><br><span style="color: hsl(120, 100%, 40%);">+first_battery=Primary</span><br><span style="color: hsl(120, 100%, 40%);">+bluetooth=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+wwan=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+wlan=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+touchpad=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+sata_mode=AHCI</span><br><span style="color: hsl(120, 100%, 40%);">+fn_ctrl_swap=Disable</span><br><span style="color: hsl(120, 100%, 40%);">+sticky_fn=Disable</span><br><span style="color: hsl(120, 100%, 40%);">+trackpoint=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+backlight=Both</span><br><span style="color: hsl(120, 100%, 40%);">+usb_always_on=Disable</span><br><span>diff --git a/src/mainboard/lenovo/t431s/cmos.layout b/src/mainboard/lenovo/t431s/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..62a6ad45</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/cmos.layout</span><br><span>@@ -0,0 +1,136 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register A</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register B</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register C</span><br><span style="color: hsl(120, 100%, 40%);">+#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#100 1 r 0 uf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#101 1 r 0 af_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#102 1 r 0 pf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#103 1 r 0 irqf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register D</span><br><span style="color: hsl(120, 100%, 40%);">+#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Diagnostic Status Register</span><br><span style="color: hsl(120, 100%, 40%);">+#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 4 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+#390 2 r 0 unused?</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+#392 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 6 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#400 8 r 0 reserved for century byte</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 7 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: EC</span><br><span style="color: hsl(120, 100%, 40%);">+411 1 e 8 first_battery</span><br><span style="color: hsl(120, 100%, 40%);">+412 1 e 1 bluetooth</span><br><span style="color: hsl(120, 100%, 40%);">+413 1 e 1 wwan</span><br><span style="color: hsl(120, 100%, 40%);">+414 1 e 1 touchpad</span><br><span style="color: hsl(120, 100%, 40%);">+415 1 e 1 wlan</span><br><span style="color: hsl(120, 100%, 40%);">+416 1 e 1 trackpoint</span><br><span style="color: hsl(120, 100%, 40%);">+417 1 e 1 fn_ctrl_swap</span><br><span style="color: hsl(120, 100%, 40%);">+418 1 e 1 sticky_fn</span><br><span style="color: hsl(120, 100%, 40%);">+419 2 e 12 usb_always_on</span><br><span style="color: hsl(120, 100%, 40%);">+421 1 e 9 sata_mode</span><br><span style="color: hsl(120, 100%, 40%);">+422 2 e 10 backlight</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: cpu</span><br><span style="color: hsl(120, 100%, 40%);">+#424 8 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+432 3 e 11 gfx_uma_size</span><br><span style="color: hsl(120, 100%, 40%);">+#435 1 e 1 enable_dual_graphics</span><br><span style="color: hsl(120, 100%, 40%);">+#436 4 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+440 8 h 0 volume</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# SandyBridge MRC Scrambler Seed values</span><br><span style="color: hsl(120, 100%, 40%);">+896 32 r 0 mrc_scrambler_seed</span><br><span style="color: hsl(120, 100%, 40%);">+928 32 r 0 mrc_scrambler_seed_s3</span><br><span style="color: hsl(120, 100%, 40%);">+960 16 r 0 mrc_scrambler_seed_chk</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+6 0 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+6 1 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+6 2 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+6 3 Error</span><br><span style="color: hsl(120, 100%, 40%);">+6 4 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+6 5 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+7 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+7 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+7 2 Keep</span><br><span style="color: hsl(120, 100%, 40%);">+8 0 Secondary</span><br><span style="color: hsl(120, 100%, 40%);">+8 1 Primary</span><br><span style="color: hsl(120, 100%, 40%);">+9 0 AHCI</span><br><span style="color: hsl(120, 100%, 40%);">+9 1 Compatible</span><br><span style="color: hsl(120, 100%, 40%);">+10 0 Both</span><br><span style="color: hsl(120, 100%, 40%);">+10 1 Keyboard only</span><br><span style="color: hsl(120, 100%, 40%);">+10 2 Thinklight only</span><br><span style="color: hsl(120, 100%, 40%);">+10 3 None</span><br><span style="color: hsl(120, 100%, 40%);">+11 0 32M</span><br><span style="color: hsl(120, 100%, 40%);">+11 1 64M</span><br><span style="color: hsl(120, 100%, 40%);">+11 2 96M</span><br><span style="color: hsl(120, 100%, 40%);">+11 3 128M</span><br><span style="color: hsl(120, 100%, 40%);">+11 4 160M</span><br><span style="color: hsl(120, 100%, 40%);">+11 5 192M</span><br><span style="color: hsl(120, 100%, 40%);">+11 6 224M</span><br><span style="color: hsl(120, 100%, 40%);">+12 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+12 1 AC and battery</span><br><span style="color: hsl(120, 100%, 40%);">+12 2 AC only</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 447 984</span><br><span>diff --git a/src/mainboard/lenovo/t431s/data.vbt b/src/mainboard/lenovo/t431s/data.vbt</span><br><span>new file mode 100644</span><br><span>index 0000000..7593154</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/data.vbt</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/lenovo/t431s/devicetree.cb b/src/mainboard/lenovo/t431s/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..a4286e6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/devicetree.cb</span><br><span>@@ -0,0 +1,193 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/sandybridge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.ndid" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable DisplayPort Hotplug with 6ms pulse</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_b_hotplug" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_c_hotplug" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_d_hotplug" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Panel as eDP and configure power delays</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_port_select" = "1" # eDP</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_up_delay" = "2000" # T1+T2: 10ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_down_delay" = "500" # T5+T6: 10ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_on_delay" = "1" # T3: 210ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_off_delay" = "1" # T4: 210ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.use_spread_spectrum_clock" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.link_frequency_270_mhz" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_cpu_backlight" = "0x03d2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_pch_backlight" = "0x11551155"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_rPGA989</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_206ax</span><br><span style="color: hsl(120, 100%, 40%);">+ # Magic APIC ID to locate this chip</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xACAC off end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pci_mmio_size" = "2048"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+ end # host bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.0 off end # PCIe Bridge for discrete graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+ end # Integrated Graphics Controller</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPI routing</span><br><span style="color: hsl(120, 100%, 40%);">+ # 0 No effect (default)</span><br><span style="color: hsl(120, 100%, 40%);">+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)</span><br><span style="color: hsl(120, 100%, 40%);">+ # 2 SCI (if corresponding GPIO_EN bit is also set)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpi1_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpi13_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x17"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set max SATA speed to 6.0 Gb/s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_interface_speed_support" = "0x3"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x7c1601"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x0c15e1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen4_dec" = "0x0c06a1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Wire port 4 (wwan usb) to ehci for it lacks superspeed components</span><br><span style="color: hsl(120, 100%, 40%);">+ register "xhci_switchable_ports" = "0x7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "superspeed_capable_ports" = "0xf"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "xhci_overcurrent_mapping" = "0x4000201"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable zero-based linear PCIe root port functions</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_port_coalesce" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "101" # c2 not supported</span><br><span style="color: hsl(120, 100%, 40%);">+ register "p_cnt_throttling_supported" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "docking_supported" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_uvscc" = "0x2005"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_lvscc" = "0x2005"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+ end # USB 3.0 Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 off end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f3</span><br><span style="color: hsl(120, 100%, 40%);">+ end # Intel Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+ end # USB Enhanced Host Controller #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+ end # High Definition Audio Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on # PCIe Port #1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/ricoh/rce822 # Ricoh cardreader</span><br><span style="color: hsl(120, 100%, 40%);">+ register "disable_mask" = "0x87"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdwppol" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on # Ricoh SD card reader</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCIe Port #2 Integrated Wireless LAN</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCIe Port #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCIe Port #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 off end # PCIe Port #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCIe Port #6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCIe Port #7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCIe Port #8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+ end # USB Enhanced Host Controller #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/lenovo/pmh7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp ff.1 on # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ register "backlight_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dock_event_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/lenovo/h8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp ff.2 on # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x62</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x64 = 0x1600</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x66 = 0x1604</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config0" = "0xa6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config1" = "0x09"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config2" = "0xa0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config3" = "0xc0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_keyboard_backlight" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "beepmask0" = "0x00"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "beepmask1" = "0x86"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_power_management_beeps" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event2_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event3_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event4_enable" = "0xd0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event5_enable" = "0x3c"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event6_enable" = "0x00"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event7_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event8_enable" = "0x7b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event9_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventa_enable" = "0x00"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventb_enable" = "0x00"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventc_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventd_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "evente_enable" = "0x1d"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # T431s only has BT on wlan card</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_bdc_detection" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+ end # 6 port SATA AHCI Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x2208</span><br><span style="color: hsl(120, 100%, 40%);">+ # eeprom, 8 virtual devices, same chip</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/at24rf08c</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 54 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 55 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 56 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 57 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5c on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5d on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5e on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5f on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # SMBus Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off end # SATA Controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/lenovo/t431s/dsdt.asl b/src/mainboard/lenovo/t431s/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..1cb4add</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/dsdt.asl</span><br><span>@@ -0,0 +1,56 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define THINKPAD_EC_GPE 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB</span><br><span style="color: hsl(120, 100%, 40%);">+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_LENOVO_H8_ME_WORKAROUND 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02, // DSDT revision: ACPI v2.0 and up</span><br><span style="color: hsl(120, 100%, 40%);">+ OEM_ID,</span><br><span style="color: hsl(120, 100%, 40%);">+ ACPI_TABLE_CREATOR,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20110725 // OEM revision</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Some generic macros</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/platform.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // global NVS and variables</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/intel/common/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/pch.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chipset specific sleep states */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/lenovo/t431s/gma-mainboard.ads b/src/mainboard/lenovo/t431s/gma-mainboard.ads</span><br><span>new file mode 100644</span><br><span>index 0000000..d635d88</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/gma-mainboard.ads</span><br><span>@@ -0,0 +1,34 @@</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- Copyright (C) 2017 Bill XIE persmule@gmail.com</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+-- it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+-- the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+-- (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+-- but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+-- GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+with HW.GFX.GMA;</span><br><span style="color: hsl(120, 100%, 40%);">+with HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+use HW.GFX.GMA;</span><br><span style="color: hsl(120, 100%, 40%);">+use HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+private package GMA.Mainboard is</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ports : constant Port_List :=</span><br><span style="color: hsl(120, 100%, 40%);">+ (DP1,</span><br><span style="color: hsl(120, 100%, 40%);">+ DP2,</span><br><span style="color: hsl(120, 100%, 40%);">+ DP3,</span><br><span style="color: hsl(120, 100%, 40%);">+ HDMI1,</span><br><span style="color: hsl(120, 100%, 40%);">+ HDMI2,</span><br><span style="color: hsl(120, 100%, 40%);">+ HDMI3,</span><br><span style="color: hsl(120, 100%, 40%);">+ Analog,</span><br><span style="color: hsl(120, 100%, 40%);">+ Internal,</span><br><span style="color: hsl(120, 100%, 40%);">+ others => Disabled);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+end GMA.Mainboard;</span><br><span>diff --git a/src/mainboard/lenovo/t431s/gpio.c b/src/mainboard/lenovo/t431s/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..5e0684c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/gpio.c</span><br><span>@@ -0,0 +1,206 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio11 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio30 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_RESET_RSMRST,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio40 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio44 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio45 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio47 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio58 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio59 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio62 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio63 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio44 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio45 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio47 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio67 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio74 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio75 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio67 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set1_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set2_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set3 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set3_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set3_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set3_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set3_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/lenovo/t431s/hda_verb.c b/src/mainboard/lenovo/t431s/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..179fba0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/hda_verb.c</span><br><span>@@ -0,0 +1,76 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10ec0269, /* Codec Vendor / Device ID: Realtek */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x17aa2208, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000000b, /* Number of 4 dword sets */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x01: Subsystem ID. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(0x0, 0x17aa2208),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x12. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x14. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x15. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x15, 0x03211020),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x17. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x17, 0x40008000),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x18. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11030),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x19. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1a. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1b. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1d. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1d, 0x40f38205),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1e. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x80862806, /* Codec Vendor / Device ID: Intel */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x80860101, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000004, /* Number of 4 dword sets */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x01: Subsystem ID. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(0x3, 0x80860101),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x05. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x06. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x07. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[0] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AZALIA_ARRAY_SIZES;</span><br><span>diff --git a/src/mainboard/lenovo/t431s/mainboard.c b/src/mainboard/lenovo/t431s/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..6c85aba</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/mainboard.c</span><br><span>@@ -0,0 +1,35 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011-2012 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/intel/gma/int15.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/lenovo/h8/h8.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,</span><br><span style="color: hsl(120, 100%, 40%);">+ GMA_INT15_PANEL_FIT_DEFAULT,</span><br><span style="color: hsl(120, 100%, 40%);">+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void h8_mainboard_init_dock(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/lenovo/t431s/romstage.c b/src/mainboard/lenovo/t431s/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..c87e218</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/romstage.c</span><br><span>@@ -0,0 +1,81 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2010 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <option.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/byteorder.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbfs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/lenovo/pmh7/pmh7.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable_lpc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* EC Decode Range Port60/64, Port62/66 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable EC, PS/2 Keyboard/Mouse */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_LPC_DEV, LPC_EN,</span><br><span style="color: hsl(120, 100%, 40%);">+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 0 }, /* SSP1: right */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 1 }, /* SSP2: left, EHCI Debug */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 3 }, /* SSP3: dock usb3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, -1 }, /* B0P4: wwan usb */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 2 }, /* B0P5: dock usb2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 0, -1 }, /* B0P6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 0, -1 }, /* B0P7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 2, -1 }, /* B0P8: unknown */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* B1P1: smart card reader */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 2, 5 }, /* B1P2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, -1 }, /* B1P3: fingerprint reader */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 0, -1 }, /* B1P4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, -1 }, /* B1P5: wlan usb */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, -1 }, /* B1P6: Camera */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_get_spd(spd_raw_data *spd, bool id_only) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t spd_file_len = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,</span><br><span style="color: hsl(120, 100%, 40%);">+ &spd_file_len);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!spd_file || spd_file_len < sizeof(spd_raw_data))</span><br><span style="color: hsl(120, 100%, 40%);">+ die("SPD data for C1S0 not found.");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&spd[0], spd_file, spd_file_len);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[2], 0x51, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_early_init(int s3resume)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_config_superio(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/lenovo/t431s/spd/Makefile.inc b/src/mainboard/lenovo/t431s/spd/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..17bb8fa</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/spd/Makefile.inc</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2016 Alexander Couzens <lynxis@fe80.eu></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_BIN = $(obj)/spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES = samsung_4gb # 0b0010 4GiB</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# Include spd ROM data</span><br><span style="color: hsl(120, 100%, 40%);">+$(SPD_BIN): $(SPD_DEPS)</span><br><span style="color: hsl(120, 100%, 40%);">+ for f in $+; \</span><br><span style="color: hsl(120, 100%, 40%);">+ do for c in $$(cat $$f | grep -v ^#); \</span><br><span style="color: hsl(120, 100%, 40%);">+ do printf $$(printf '\%o' 0x$$c); \</span><br><span style="color: hsl(120, 100%, 40%);">+ done; \</span><br><span style="color: hsl(120, 100%, 40%);">+ done > $@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+cbfs-files-y += spd.bin</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-file := $(SPD_BIN)</span><br><span style="color: hsl(120, 100%, 40%);">+spd.bin-type := spd</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex b/src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex</span><br><span>new file mode 100644</span><br><span>index 0000000..252ff3f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/spd/samsung_4gb.spd.hex</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+92 11 0b 03 04 00 00 01 03 52 01 08 0a 00 80 00 </span><br><span style="color: hsl(120, 100%, 40%);">+6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 b6 3b </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 </span><br><span style="color: hsl(120, 100%, 40%);">+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/lenovo/t431s/thermal.h b/src/mainboard/lenovo/t431s/thermal.h</span><br><span>new file mode 100644</span><br><span>index 0000000..1d55584</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t431s/thermal.h</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef T430S_THERMAL_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define T430S_THERMAL_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Temperature which OS will shutdown at */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CRITICAL_TEMPERATURE 100</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Temperature which OS will throttle CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PASSIVE_TEMPERATURE 90</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* T430S_THERMAL_H */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30021">change 30021</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30021"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a </div>
<div style="display:none"> Gerrit-Change-Number: 30021 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Bill XIE <persmule@gmail.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>