[coreboot-gerrit] Change in ...coreboot[master]: sb/amd/sr5650/cmn.h: Don't use device_t
HAOUAS Elyes (Code Review)
gerrit at coreboot.org
Sun Dec 2 21:39:59 CET 2018
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30007
Change subject: sb/amd/sr5650/cmn.h: Don't use device_t
......................................................................
sb/amd/sr5650/cmn.h: Don't use device_t
Use of device_t is deprecated.
Change-Id: Iddbec373bfb3f8dc208397727de32db3844a333a
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/amd/sr5650/cmn.h
1 file changed, 140 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/30007/1
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h
index 859e15d..f5047d9 100644
--- a/src/southbridge/amd/sr5650/cmn.h
+++ b/src/southbridge/amd/sr5650/cmn.h
@@ -34,30 +34,32 @@
#define AB_INDX 0xCD8
#define AB_DATA (AB_INDX+4)
-static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
+#ifdef __SIMPLE_DEVICE__
+static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)
{
pci_write_config32(dev, index_reg, index);
return pci_read_config32(dev, index_reg + 0x4);
}
-static inline void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
+static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index,
+ u32 data)
{
pci_write_config32(dev, index_reg, index);
pci_write_config32(dev, index_reg + 0x4, data);
}
-static inline u32 nbmisc_read_index(device_t nb_dev, u32 index)
+static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
{
return nb_read_index((nb_dev), NBMISC_INDEX, (index));
}
-static inline void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
+static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
{
nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
}
-static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
- u32 val)
+static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
{
u32 reg_old, reg;
reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
@@ -68,28 +70,28 @@
}
}
-static inline u32 htiu_read_index(device_t nb_dev, u32 index)
+static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
{
return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
}
-static inline void htiu_write_index(device_t nb_dev, u32 index, u32 data)
+static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
{
nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
}
-static inline u32 nbmc_read_index(device_t nb_dev, u32 index)
+static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
{
return nb_read_index((nb_dev), NBMC_INDEX, (index));
}
-static inline void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
+static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
{
nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
}
-static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
- u32 val)
+static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
{
u32 reg_old, reg;
reg = reg_old = htiu_read_index(nb_dev, reg_pos);
@@ -100,8 +102,8 @@
}
}
-static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
- u32 val)
+static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
{
u32 reg_old, reg;
reg = reg_old = pci_read_config32(nb_dev, reg_pos);
@@ -112,8 +114,8 @@
}
}
-static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,
- u8 val)
+static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos,
+ u8 mask, u8 val)
{
u8 reg_old, reg;
reg = reg_old = pci_read_config8(nb_dev, reg_pos);
@@ -124,8 +126,8 @@
}
}
-static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
- u32 val)
+static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
{
u32 reg_old, reg;
reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
@@ -136,7 +138,8 @@
}
}
-static inline void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
+static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask,
+ u32 val)
{
u32 reg_old, reg;
reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
@@ -147,6 +150,124 @@
}
}
+#else
+static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index)
+{
+ pci_write_config32(dev, index_reg, index);
+ return pci_read_config32(dev, index_reg + 0x4);
+}
+
+static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index,
+ u32 data)
+{
+ pci_write_config32(dev, index_reg, index);
+ pci_write_config32(dev, index_reg + 0x4, data);
+}
+
+static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index)
+{
+ return nb_read_index((nb_dev), NBMISC_INDEX, (index));
+}
+
+static inline void nbmisc_write_index(struct device *nb_dev, u32 index,
+ u32 data)
+{
+ nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
+}
+
+static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ nbmisc_write_index(nb_dev, reg_pos, reg);
+ }
+}
+
+static inline u32 htiu_read_index(struct device *nb_dev, u32 index)
+{
+ return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
+}
+
+static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data)
+{
+ nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
+}
+
+static inline u32 nbmc_read_index(struct device *nb_dev, u32 index)
+{
+ return nb_read_index((nb_dev), NBMC_INDEX, (index));
+}
+
+static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data)
+{
+ nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
+}
+
+static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = htiu_read_index(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ htiu_write_index(nb_dev, reg_pos, reg);
+ }
+}
+
+static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = pci_read_config32(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ pci_write_config32(nb_dev, reg_pos, reg);
+ }
+}
+
+static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos,
+ u8 mask, u8 val)
+{
+ u8 reg_old, reg;
+ reg = reg_old = pci_read_config8(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ pci_write_config8(nb_dev, reg_pos, reg);
+ }
+}
+
+static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ nbmc_write_index(nb_dev, reg_pos, reg);
+ }
+}
+
+static inline void set_pcie_enable_bits(struct device *dev, u32 reg_pos,
+ u32 mask, u32 val)
+{
+ u32 reg_old, reg;
+ reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
+ reg &= ~mask;
+ reg |= val;
+ if (reg != reg_old) {
+ nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg);
+ }
+}
+#endif /* __SIMPLE_DEVICE__ */
+
void set_pcie_reset(void);
void set_pcie_dereset(void);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iddbec373bfb3f8dc208397727de32db3844a333a
Gerrit-Change-Number: 30007
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes <ehaouas at noos.fr>
Gerrit-MessageType: newchange
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