[coreboot-gerrit] Change in coreboot[master]: cpu/intel/smm: Don't make assumptions on TSEG_SIZE

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27872


Change subject: cpu/intel/smm: Don't make assumptions on TSEG_SIZE
......................................................................

cpu/intel/smm: Don't make assumptions on TSEG_SIZE

Do not assume:
- TSEG is 8M
- IED_REGION_SIZE is set (not needed on older platforms).

Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/smm/gen1/smmrelocate.c
1 file changed, 21 insertions(+), 10 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27872/1

diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index a298985..aa689f0 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -16,6 +16,7 @@
 /* SMM relocation with intention to work for i945-ivybridge.
    Right now used for sandybridge and ivybridge.  */
 
+#include <assert.h>
 #include <types.h>
 #include <string.h>
 #include <compiler.h>
@@ -125,10 +126,15 @@
 	 * size * CPU num. */
 	save_state->smbase = relo_params->smram_base -
 			     cpu * runtime->save_state_size;
-	save_state->iedbase = relo_params->ied_base;
+	if (CONFIG_IED_REGION_SIZE != 0) {
+		save_state->iedbase = relo_params->ied_base;
 
-	printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",
-	       save_state->smbase, save_state->iedbase, save_state);
+		printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",
+		       save_state->smbase, save_state->iedbase, save_state);
+	} else {
+		printk(BIOS_DEBUG, "New SMBASE=0x%08x @ %p\n",
+		       save_state->smbase, save_state);
+	}
 
 	/* Write SMRR MSRs based on indicated support. */
 	mtrr_cap = rdmsr(MTRR_CAP_MSR);
@@ -149,16 +155,20 @@
 	   configuration value instead. */
 	const u32 tseg_size = northbridge_get_tseg_size();
 
-	/* The SMRAM available to the handler is 4MiB
-	   since the IEDRAM lives at TSEGMB + 4MiB. */
 	params->smram_base = tsegmb;
-	params->smram_size = 4 << 20;
-	params->ied_base = tsegmb + params->smram_size;
-	params->ied_size = tseg_size - params->smram_size;
+	params->smram_size = tseg_size;
+	if (CONFIG_IED_REGION_SIZE != 0) {
+		ASSERT(CONFIG_IED_REGION_SIZE > params->smram_size);
+		params->smram_size -= CONFIG_IED_REGION_SIZE;
+		params->ied_base = tsegmb + tseg_size - CONFIG_IED_REGION_SIZE;
+		params->ied_size = CONFIG_IED_REGION_SIZE;
+	}
 
 	/* Adjust available SMM handler memory size. */
-	if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM))
+	if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {
+		ASSERT(CONFIG_SMM_RESERVED_SIZE > params->smram_size);
 		params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
+	}
 
 	if (IS_ALIGNED(tsegmb, tseg_size)) {
 		/* SMRR has 32-bits of valid address aligned to 4KiB. */
@@ -264,7 +274,8 @@
 	/* enable the SMM memory window */
 	northbridge_write_smram(D_OPEN | G_SMRAME | C_BASE_SEG);
 
-	setup_ied_area(&smm_reloc_params);
+	if (CONFIG_IED_REGION_SIZE != 0)
+		setup_ied_area(&smm_reloc_params);
 
 	num_cpus = cpu_get_apic_id_map(apic_id_map);
 	if (num_cpus > CONFIG_MAX_CPUS) {

-- 
To view, visit https://review.coreboot.org/27872
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a
Gerrit-Change-Number: 27872
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180806/526830fc/attachment.html>