<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27872">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/smm: Don't make assumptions on TSEG_SIZE<br><br>Do not assume:<br>- TSEG is 8M<br>- IED_REGION_SIZE is set (not needed on older platforms).<br><br>Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/smm/gen1/smmrelocate.c<br>1 file changed, 21 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27872/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>index a298985..aa689f0 100644</span><br><span>--- a/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>+++ b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>@@ -16,6 +16,7 @@</span><br><span> /* SMM relocation with intention to work for i945-ivybridge.</span><br><span>    Right now used for sandybridge and ivybridge.  */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span> #include <types.h></span><br><span> #include <string.h></span><br><span> #include <compiler.h></span><br><span>@@ -125,10 +126,15 @@</span><br><span>   * size * CPU num. */</span><br><span>        save_state->smbase = relo_params->smram_base -</span><br><span>                              cpu * runtime->save_state_size;</span><br><span style="color: hsl(0, 100%, 40%);">- save_state->iedbase = relo_params->ied_base;</span><br><span style="color: hsl(120, 100%, 40%);">+    if (CONFIG_IED_REGION_SIZE != 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+            save_state->iedbase = relo_params->ied_base;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-  printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",</span><br><span style="color: hsl(0, 100%, 40%);">-        save_state->smbase, save_state->iedbase, save_state);</span><br><span style="color: hsl(120, 100%, 40%);">+            printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",</span><br><span style="color: hsl(120, 100%, 40%);">+                      save_state->smbase, save_state->iedbase, save_state);</span><br><span style="color: hsl(120, 100%, 40%);">+    } else {</span><br><span style="color: hsl(120, 100%, 40%);">+              printk(BIOS_DEBUG, "New SMBASE=0x%08x @ %p\n",</span><br><span style="color: hsl(120, 100%, 40%);">+                     save_state->smbase, save_state);</span><br><span style="color: hsl(120, 100%, 40%);">+    }</span><br><span> </span><br><span>        /* Write SMRR MSRs based on indicated support. */</span><br><span>    mtrr_cap = rdmsr(MTRR_CAP_MSR);</span><br><span>@@ -149,16 +155,20 @@</span><br><span>         configuration value instead. */</span><br><span>   const u32 tseg_size = northbridge_get_tseg_size();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-  /* The SMRAM available to the handler is 4MiB</span><br><span style="color: hsl(0, 100%, 40%);">-      since the IEDRAM lives at TSEGMB + 4MiB. */</span><br><span>       params->smram_base = tsegmb;</span><br><span style="color: hsl(0, 100%, 40%);">- params->smram_size = 4 << 20;</span><br><span style="color: hsl(0, 100%, 40%);">-  params->ied_base = tsegmb + params->smram_size;</span><br><span style="color: hsl(0, 100%, 40%);">-   params->ied_size = tseg_size - params->smram_size;</span><br><span style="color: hsl(120, 100%, 40%);">+      params->smram_size = tseg_size;</span><br><span style="color: hsl(120, 100%, 40%);">+    if (CONFIG_IED_REGION_SIZE != 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+            ASSERT(CONFIG_IED_REGION_SIZE > params->smram_size);</span><br><span style="color: hsl(120, 100%, 40%);">+            params->smram_size -= CONFIG_IED_REGION_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+              params->ied_base = tsegmb + tseg_size - CONFIG_IED_REGION_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+            params->ied_size = CONFIG_IED_REGION_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span>        /* Adjust available SMM handler memory size. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM))</span><br><span style="color: hsl(120, 100%, 40%);">+        if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {</span><br><span style="color: hsl(120, 100%, 40%);">+              ASSERT(CONFIG_SMM_RESERVED_SIZE > params->smram_size);</span><br><span>                 params->smram_size -= CONFIG_SMM_RESERVED_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+    }</span><br><span> </span><br><span>        if (IS_ALIGNED(tsegmb, tseg_size)) {</span><br><span>                 /* SMRR has 32-bits of valid address aligned to 4KiB. */</span><br><span>@@ -264,7 +274,8 @@</span><br><span>       /* enable the SMM memory window */</span><br><span>   northbridge_write_smram(D_OPEN | G_SMRAME | C_BASE_SEG);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-    setup_ied_area(&smm_reloc_params);</span><br><span style="color: hsl(120, 100%, 40%);">+        if (CONFIG_IED_REGION_SIZE != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+              setup_ied_area(&smm_reloc_params);</span><br><span> </span><br><span>   num_cpus = cpu_get_apic_id_map(apic_id_map);</span><br><span>         if (num_cpus > CONFIG_MAX_CPUS) {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27872">change 27872</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27872"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a </div>
<div style="display:none"> Gerrit-Change-Number: 27872 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>