[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Update UPD from device switch
Lijian Zhao (Code Review)
gerrit at coreboot.org
Wed Aug 1 02:29:25 CEST 2018
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/27766
Change subject: soc/intel/cannonlake: Update UPD from device switch
......................................................................
soc/intel/cannonlake: Update UPD from device switch
Some of the FSP silicon UPD entry can be updated base on device switch
in pci device tree, have both static config setting and device tree "on"
and "off" will be redundant.
BUG=N/A
TEST=Build and boot up fine with Whiskey Lake RVP platform.
Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
M src/mainboard/google/zoombini/variants/meowth/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
9 files changed, 40 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/27766/1
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
index 479f280..f993ae9 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
@@ -21,9 +21,7 @@
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
- register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
- register "ScsSdCardEnabled" = "1"
# Intel Common SoC Config
#+-------------------+---------------------------+
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
index bbff695..ef40ccc 100644
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
@@ -30,9 +30,7 @@
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "SmbusEnable" = "1"
- register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
- register "ScsSdCardEnabled" = "1"
# Intel Common SoC Config
#+-------------------+---------------------------+
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index 6bd90a5..3357140 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -7,9 +7,7 @@
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
- register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
- register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 4c62800..02d6b70 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -7,9 +7,7 @@
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
- register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
- register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
index 9414b32..de316ca 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
@@ -7,9 +7,7 @@
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
- register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
- register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb
index 5bebdec..45877f4 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb
@@ -7,9 +7,7 @@
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
- register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
- register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb
index 62a6635..7e5cd60 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb
@@ -7,9 +7,7 @@
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
- register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
- register "ScsSdCardEnabled" = "1"
register "HeciEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
@@ -30,7 +28,6 @@
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
- register "SataEnable" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 30719ed..6768057 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -208,16 +208,25 @@
params->PchLockDownRtcMemoryLock = 0;
/* SATA */
- params->SataEnable = config->SataEnable;
- params->SataMode = config->SataMode;
- params->SataSalpSupport = config->SataSalpSupport;
- memcpy(params->SataPortsEnable, config->SataPortsEnable,
+ dev = dev_find_slot(0, PCH_DEVFN_SATA);
+ if (!dev)
+ params->SataEnable = 0;
+ else {
+ params->SataEnable = dev->enabled;
+ params->SataMode = config->SataMode;
+ params->SataSalpSupport = config->SataSalpSupport;
+ memcpy(params->SataPortsEnable, config->SataPortsEnable,
sizeof(params->SataPortsEnable));
- memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
+ memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
sizeof(params->SataPortsDevSlp));
+ }
/* Lan */
- params->PchLanEnable = config->PchLanEnable;
+ dev = dev_find_slot(0, PCH_DEVFN_GBE);
+ if (!dev)
+ params->PchLanEnable = 0;
+ else
+ params->PchLanEnable = dev->enabled;
/* Audio */
params->PchHdaDspEnable = config->PchHdaDspEnable;
@@ -283,16 +292,32 @@
sizeof(config->PcieClkSrcClkReq));
/* eMMC and SD */
- params->ScsEmmcEnabled = config->ScsEmmcEnabled;
- params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
- params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
- if (config->EmmcHs400DllNeed == 1) {
- params->PchScsEmmcHs400RxStrobeDll1 =
- config->EmmcHs400RxStrobeDll1;
- params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll;
+ dev = dev_find_slot(0, PCH_DEVFN_EMMC);
+ if (!dev)
+ params->ScsEmmcEnabled = 0;
+ else {
+ params->ScsEmmcEnabled = dev->enabled;
+ params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
+ params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
+ if (config->EmmcHs400DllNeed == 1) {
+ params->PchScsEmmcHs400RxStrobeDll1 =
+ config->EmmcHs400RxStrobeDll1;
+ params->PchScsEmmcHs400TxDataDll =
+ config->EmmcHs400TxDataDll;
+ }
}
- params->ScsSdCardEnabled = config->ScsSdCardEnabled;
- params->ScsUfsEnabled = config->ScsUfsEnabled;
+
+ dev = dev_find_slot(0, PCH_DEVFN_SDCARD);
+ if (!dev)
+ params->ScsSdCardEnabled = 0;
+ else
+ params->ScsSdCardEnabled = dev->enabled;
+
+ dev = dev_find_slot(0, PCH_DEVFN_UFS);
+ if (!dev)
+ params->ScsUfsEnabled = 0;
+ else
+ params->ScsUfsEnabled = dev->enabled;
params->Heci3Enabled = config->Heci3Enabled;
params->Device4Enable = config->Device4Enable;
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 4704d1c..e018cab 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -118,9 +118,6 @@
/* Rank Margin Tool. 1:Enable, 0:Disable */
uint8_t RMT;
- /* LAN controller. 1:Enable, 0:Disable */
- uint8_t PchLanEnable;
-
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];
@@ -130,9 +127,7 @@
/* Wake Enable Bitmap for USB3 ports */
uint16_t usb3_wake_enable_bitmap;
-
/* SATA related */
- uint8_t SataEnable;
uint8_t SataMode;
uint8_t SataSalpSupport;
uint8_t SataPortsEnable[8];
@@ -168,7 +163,6 @@
uint8_t SmbusEnable;
/* eMMC and SD */
- uint8_t ScsEmmcEnabled;
uint8_t ScsEmmcHs400Enabled;
/* Need to update DLL setting to get Emmc running at HS400 speed */
uint8_t EmmcHs400DllNeed;
@@ -176,8 +170,6 @@
uint8_t EmmcHs400RxStrobeDll1;
/* 0-78: number of active delay for TX data, unit is 125 psec */
uint8_t EmmcHs400TxDataDll;
- uint8_t ScsSdCardEnabled;
- uint8_t ScsUfsEnabled;
/* Integrated Sensor */
uint8_t PchIshEnable;
--
To view, visit https://review.coreboot.org/27766
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9
Gerrit-Change-Number: 27766
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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