<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27766">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Update UPD from device switch<br><br>Some of the FSP silicon UPD entry can be updated base on device switch<br>in pci device tree, have both static config setting and device tree "on"<br>and "off" will be redundant.<br><br>BUG=N/A<br>TEST=Build and boot up fine with Whiskey Lake RVP platform.<br><br>Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb<br>M src/mainboard/google/zoombini/variants/meowth/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb<br>M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb<br>M src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb<br>M src/soc/intel/cannonlake/chip.c<br>M src/soc/intel/cannonlake/chip.h<br>9 files changed, 40 insertions(+), 38 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/27766/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>index 479f280..f993ae9 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>@@ -21,9 +21,7 @@</span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span> register "SmbusEnable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsEmmcEnabled" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsSdCardEnabled" = "1"</span><br><span> </span><br><span> # Intel Common SoC Config</span><br><span> #+-------------------+---------------------------+</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>index bbff695..ef40ccc 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>@@ -30,9 +30,7 @@</span><br><span> # FSP configuration</span><br><span> register "SaGv" = "SaGv_Enabled"</span><br><span> register "SmbusEnable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsEmmcEnabled" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsSdCardEnabled" = "1"</span><br><span> </span><br><span> # Intel Common SoC Config</span><br><span> #+-------------------+---------------------------+</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>index 6bd90a5..3357140 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>@@ -7,9 +7,7 @@</span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span> register "SmbusEnable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsEmmcEnabled" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsSdCardEnabled" = "1"</span><br><span> </span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span> register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>index 4c62800..02d6b70 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>@@ -7,9 +7,7 @@</span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span> register "SmbusEnable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsEmmcEnabled" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsSdCardEnabled" = "1"</span><br><span> </span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span> register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>index 9414b32..de316ca 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>@@ -7,9 +7,7 @@</span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span> register "SmbusEnable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsEmmcEnabled" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsSdCardEnabled" = "1"</span><br><span> </span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span> register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb</span><br><span>index 5bebdec..45877f4 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb</span><br><span>@@ -7,9 +7,7 @@</span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span> register "SmbusEnable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsEmmcEnabled" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsSdCardEnabled" = "1"</span><br><span> </span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span> register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb</span><br><span>index 62a6635..7e5cd60 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb</span><br><span>@@ -7,9 +7,7 @@</span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span> register "SmbusEnable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsEmmcEnabled" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "ScsSdCardEnabled" = "1"</span><br><span> register "HeciEnabled" = "1"</span><br><span> </span><br><span> register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"</span><br><span>@@ -30,7 +28,6 @@</span><br><span> register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span> register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- register "SataEnable" = "1"</span><br><span> register "SataSalpSupport" = "1"</span><br><span> register "SataPortsEnable[0]" = "1"</span><br><span> register "SataPortsEnable[1]" = "1"</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index 30719ed..6768057 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -208,16 +208,25 @@</span><br><span> params->PchLockDownRtcMemoryLock = 0;</span><br><span> </span><br><span> /* SATA */</span><br><span style="color: hsl(0, 100%, 40%);">- params->SataEnable = config->SataEnable;</span><br><span style="color: hsl(0, 100%, 40%);">- params->SataMode = config->SataMode;</span><br><span style="color: hsl(0, 100%, 40%);">- params->SataSalpSupport = config->SataSalpSupport;</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(params->SataPortsEnable, config->SataPortsEnable,</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, PCH_DEVFN_SATA);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SataEnable = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ else {</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SataEnable = dev->enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SataMode = config->SataMode;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->SataSalpSupport = config->SataSalpSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(params->SataPortsEnable, config->SataPortsEnable,</span><br><span> sizeof(params->SataPortsEnable));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,</span><br><span> sizeof(params->SataPortsDevSlp));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> /* Lan */</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchLanEnable = config->PchLanEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, PCH_DEVFN_GBE);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchLanEnable = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchLanEnable = dev->enabled;</span><br><span> </span><br><span> /* Audio */</span><br><span> params->PchHdaDspEnable = config->PchHdaDspEnable;</span><br><span>@@ -283,16 +292,32 @@</span><br><span> sizeof(config->PcieClkSrcClkReq));</span><br><span> </span><br><span> /* eMMC and SD */</span><br><span style="color: hsl(0, 100%, 40%);">- params->ScsEmmcEnabled = config->ScsEmmcEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">- params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->EmmcHs400DllNeed == 1) {</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchScsEmmcHs400RxStrobeDll1 =</span><br><span style="color: hsl(0, 100%, 40%);">- config->EmmcHs400RxStrobeDll1;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll;</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, PCH_DEVFN_EMMC);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ScsEmmcEnabled = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ else {</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ScsEmmcEnabled = dev->enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->EmmcHs400DllNeed == 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchScsEmmcHs400RxStrobeDll1 =</span><br><span style="color: hsl(120, 100%, 40%);">+ config->EmmcHs400RxStrobeDll1;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchScsEmmcHs400TxDataDll =</span><br><span style="color: hsl(120, 100%, 40%);">+ config->EmmcHs400TxDataDll;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- params->ScsSdCardEnabled = config->ScsSdCardEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">- params->ScsUfsEnabled = config->ScsUfsEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, PCH_DEVFN_SDCARD);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ScsSdCardEnabled = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ScsSdCardEnabled = dev->enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, PCH_DEVFN_UFS);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ScsUfsEnabled = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ params->ScsUfsEnabled = dev->enabled;</span><br><span> </span><br><span> params->Heci3Enabled = config->Heci3Enabled;</span><br><span> params->Device4Enable = config->Device4Enable;</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h</span><br><span>index 4704d1c..e018cab 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.h</span><br><span>+++ b/src/soc/intel/cannonlake/chip.h</span><br><span>@@ -118,9 +118,6 @@</span><br><span> /* Rank Margin Tool. 1:Enable, 0:Disable */</span><br><span> uint8_t RMT;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* LAN controller. 1:Enable, 0:Disable */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t PchLanEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* USB related */</span><br><span> struct usb2_port_config usb2_ports[16];</span><br><span> struct usb3_port_config usb3_ports[10];</span><br><span>@@ -130,9 +127,7 @@</span><br><span> /* Wake Enable Bitmap for USB3 ports */</span><br><span> uint16_t usb3_wake_enable_bitmap;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* SATA related */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t SataEnable;</span><br><span> uint8_t SataMode;</span><br><span> uint8_t SataSalpSupport;</span><br><span> uint8_t SataPortsEnable[8];</span><br><span>@@ -168,7 +163,6 @@</span><br><span> uint8_t SmbusEnable;</span><br><span> </span><br><span> /* eMMC and SD */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t ScsEmmcEnabled;</span><br><span> uint8_t ScsEmmcHs400Enabled;</span><br><span> /* Need to update DLL setting to get Emmc running at HS400 speed */</span><br><span> uint8_t EmmcHs400DllNeed;</span><br><span>@@ -176,8 +170,6 @@</span><br><span> uint8_t EmmcHs400RxStrobeDll1;</span><br><span> /* 0-78: number of active delay for TX data, unit is 125 psec */</span><br><span> uint8_t EmmcHs400TxDataDll;</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t ScsSdCardEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t ScsUfsEnabled;</span><br><span> </span><br><span> /* Integrated Sensor */</span><br><span> uint8_t PchIshEnable;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27766">change 27766</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9 </div>
<div style="display:none"> Gerrit-Change-Number: 27766 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>