[coreboot-gerrit] Change in coreboot[master]: mainboard/{google/intel}: Set FspSkipMpInit=0 to run CPU programming ...

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/25923


Change subject: mainboard/{google/intel}: Set FspSkipMpInit=0 to run CPU programming on APs
......................................................................

mainboard/{google/intel}: Set FspSkipMpInit=0 to run CPU programming on APs

This patch ensures that FSP can make use of PPI infrastructure in order
to run closed source CPU feature programming over APs during FSP-Silicon
initialization.

BRANCH=none
BUG=b:74436746
TEST=Verify CPU feature programming is using coreboot APIs.

Change-Id: I5f3144213127cc3eded93445083f6eab7dc75297
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
M src/mainboard/google/zoombini/variants/meowth/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
4 files changed, 4 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/25923/1

diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
index 512354e..f336d91 100644
--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
@@ -20,7 +20,7 @@
 
 	# FSP configuration
 	register "SaGv" = "3"
-	register "FspSkipMpInit" = "1"
+	register "FspSkipMpInit" = "0"
 	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
index 4076ea6..6a20f1c 100644
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
@@ -29,7 +29,7 @@
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
-	register "FspSkipMpInit" = "1"
+	register "FspSkipMpInit" = "0"
 	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index 18aa65d..e1b45d9 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -6,7 +6,7 @@
 
 	# FSP configuration
 	register "SaGv" = "3"
-	register "FspSkipMpInit" = "1"
+	register "FspSkipMpInit" = "0"
 	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 8bcb850..9b19a90 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -6,7 +6,7 @@
 
 	# FSP configuration
 	register "SaGv" = "3"
-	register "FspSkipMpInit" = "1"
+	register "FspSkipMpInit" = "0"
 	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5f3144213127cc3eded93445083f6eab7dc75297
Gerrit-Change-Number: 25923
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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