<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25923">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/{google/intel}: Set FspSkipMpInit=0 to run CPU programming on APs<br><br>This patch ensures that FSP can make use of PPI infrastructure in order<br>to run closed source CPU feature programming over APs during FSP-Silicon<br>initialization.<br><br>BRANCH=none<br>BUG=b:74436746<br>TEST=Verify CPU feature programming is using coreboot APIs.<br><br>Change-Id: I5f3144213127cc3eded93445083f6eab7dc75297<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb<br>M src/mainboard/google/zoombini/variants/meowth/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>4 files changed, 4 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/25923/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>index 512354e..f336d91 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>@@ -20,7 +20,7 @@</span><br><span> </span><br><span>         # FSP configuration</span><br><span>  register "SaGv" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">-       register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "FspSkipMpInit" = "0"</span><br><span>   register "SmbusEnable" = "1"</span><br><span>     register "ScsEmmcEnabled" = "1"</span><br><span>  register "ScsEmmcHs400Enabled" = "1"</span><br><span>diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>index 4076ea6..6a20f1c 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb</span><br><span>@@ -29,7 +29,7 @@</span><br><span> </span><br><span>    # FSP configuration</span><br><span>  register "SaGv" = "SaGv_Enabled"</span><br><span style="color: hsl(0, 100%, 40%);">-    register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "FspSkipMpInit" = "0"</span><br><span>   register "SmbusEnable" = "1"</span><br><span>     register "ScsEmmcEnabled" = "1"</span><br><span>  register "ScsEmmcHs400Enabled" = "1"</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>index 18aa65d..e1b45d9 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb</span><br><span>@@ -6,7 +6,7 @@</span><br><span> </span><br><span>      # FSP configuration</span><br><span>  register "SaGv" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">-       register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "FspSkipMpInit" = "0"</span><br><span>   register "SmbusEnable" = "1"</span><br><span>     register "ScsEmmcEnabled" = "1"</span><br><span>  register "ScsEmmcHs400Enabled" = "1"</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>index 8bcb850..9b19a90 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb</span><br><span>@@ -6,7 +6,7 @@</span><br><span> </span><br><span>      # FSP configuration</span><br><span>  register "SaGv" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">-       register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+    register "FspSkipMpInit" = "0"</span><br><span>   register "SmbusEnable" = "1"</span><br><span>     register "ScsEmmcEnabled" = "1"</span><br><span>  register "ScsEmmcHs400Enabled" = "1"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25923">change 25923</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25923"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5f3144213127cc3eded93445083f6eab7dc75297 </div>
<div style="display:none"> Gerrit-Change-Number: 25923 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>