[coreboot-gerrit] New patch to review for coreboot: intel/skylake: Add function to read state of Deep S5

[Duncan Laurie (dlaurie@chromium.org)]

Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18663

-gerrit

commit 7071daa5da76422d99864296f6a31938aeb5ffff
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Mar 7 19:03:50 2017 -0800

    intel/skylake: Add function to read state of Deep S5
    
    Add a function to read the current state of Deep S5 configuration
    and indicate if it is enabled (for AC and/or DC) or disabled.
    
    This is similar to the existing function that checks Deep S3
    enable state.
    
    BUG=b:36042662
    BRANCH=none
    TEST=tested with subsequent commits to check Deep S5 state at boot
    and filter event log messages if it is enabled.
    
    Change-Id: I4b60fb99a99952cb3ca6be29f257bb5894ff5a52
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/include/soc/pm.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 0045fa0..7112c77 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -198,4 +198,12 @@ static inline int deep_s3_enabled(void)
 	return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
 }
 
+static inline int deep_s5_enabled(void)
+{
+	uint32_t deep_s5_pol;
+
+	deep_s5_pol = read32(pmc_mmio_regs() + S5_PWRGATE_POL);
+	return !!(deep_s5_pol & (S5DC_GATE_SUS | S5AC_GATE_SUS));
+}
+
 #endif