[coreboot-gerrit] New patch to review for coreboot: intel/skylake: Add devicetree settings for acoustic noise mitigation

[Duncan Laurie (dlaurie@chromium.org)]

Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18662

-gerrit

commit 669dfcacff1d02f9498829a96f75eb0dcfe93690
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Mar 7 19:12:02 2017 -0800

    intel/skylake: Add devicetree settings for acoustic noise mitigation
    
    Add options to the skylake chip config that will allow tuning the
    various settings that can affect acoustics with the CPU and its VRs.
    
    These settings are applied inside FSP, and they can adjust the slew
    slew rate when changing voltages or disable fast C-state ramping on
    the various CPU VR rails.
    
    BUG=b:35581264
    BRANCH=none
    TEST=these are currently unused, but I verified that enabling the
    options can affect the acoustics of a system at runtime.
    
    Change-Id: I6a8ec0b8d3bd38b330cb4836bfa5bbbfc87dc3fb
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/chip.h       | 29 +++++++++++++++++++++++++++++
 src/soc/intel/skylake/chip_fsp20.c |  9 +++++++++
 2 files changed, 38 insertions(+)

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 7dda76a..69b5364 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -418,6 +418,35 @@ struct soc_intel_skylake_config {
 
 	/* Wake Enable Bitmap for USB3 ports */
 	u8 usb3_wake_enable_bitmap;
+
+	/*
+	 * Acoustic Noise Mitigation
+	 * 0b - Disable
+	 * 1b - Enable noise mitigation
+	 */
+	u8 AcousticNoiseMitigation;
+
+	/*
+	 * Disable Fast Package C-state ramping
+	 * Need to set AcousticNoiseMitigation = '1' first
+	 * 0b - Enabled
+	 * 1b - Disabled
+	 */
+	u8 FastPkgCRampDisableIa;
+	u8 FastPkgCRampDisableGt;
+	u8 FastPkgCRampDisableSa;
+
+	/*
+	 * Adjust the VR slew rates
+	 * Need to set AcousticNoiseMitigation = '1' first
+	 * 000b - Fast/2
+	 * 001b - Fast/4
+	 * 010b - Fast/8
+	 * 011b - Fast/16
+	 */
+	u8 SlowSlewRateForIa;
+	u8 SlowSlewRateForGt;
+	u8 SlowSlewRateForSa;
 };
 
 typedef struct soc_intel_skylake_config config_t;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 929aa5b..21d895e 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -249,6 +249,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	 */
 	params->SendVrMbxCmd1 = config->SendVrMbxCmd;
 
+	/* Acoustic Noise Mitigation */
+	params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
+	params->SlowSlewRateForIa = config->SlowSlewRateForIa;
+	params->SlowSlewRateForGt = config->SlowSlewRateForGt;
+	params->SlowSlewRateForSa = config->SlowSlewRateForSa;
+	params->FastPkgCRampDisableIa = config->FastPkgCRampDisableIa;
+	params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt;
+	params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
+
 	soc_irq_settings(params);
 }