[coreboot-gerrit] New patch to review for coreboot: google/eve: Configure GPIOs for new board

[Duncan Laurie (dlaurie@chromium.org)]

Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18661

-gerrit

commit a16c19534cd59e97a5bde8c74a020784b2e30e12
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Mar 7 18:59:19 2017 -0800

    google/eve: Configure GPIOs for new board
    
    A new board revision is making use of two previously unused GPIOs
    to drive BOOT/RESET pins to an on-board MCU.
    
    The reset pin is open drain so it is set as input by default, and
    the boot pin is driven low by default.
    
    Since these are UART0 pins they also need to be set up again after
    executing FSP-S as it will change them back to native mode pins.
    
    BUG=b:36025702
    BRANCH=none
    TEST=manual testing on reworked board, toggling GPIOs to put
    the MCU into programming mode.
    
    Change-Id: Id6f0ef2f863bc1e873b58e344446038786b59d25
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/eve/gpio.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h
index 85011f1..deb0192 100644
--- a/src/mainboard/google/eve/gpio.h
+++ b/src/mainboard/google/eve/gpio.h
@@ -105,8 +105,8 @@ static const struct pad_config gpio_table[] = {
 /* SM1DATA */		PAD_CFG_NC(GPP_C7),
 /* UART0_RXD */		PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */
 /* UART0_TXD */		PAD_CFG_GPO(GPP_C9, 1, DEEP), /* FP_RST_ODL */
-/* UART0_RTS# */	PAD_CFG_NC(GPP_C10),
-/* UART0_CTS# */	PAD_CFG_NC(GPP_C11),
+/* UART0_RTS# */	PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */
+/* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FPS_MCU_BOOT0 */
 /* UART1_RXD */		PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
 /* UART1_TXD */		PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
 /* UART1_RTS# */	PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
@@ -234,6 +234,8 @@ static const struct pad_config early_gpio_table[] = {
 static const struct pad_config late_gpio_table[] = {
 /* UART0_RXD */		PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */
 /* UART0_TXD */		PAD_CFG_GPO(GPP_C9, 1, DEEP), /* FP_RST_ODL */
+/* UART0_RTS# */	PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */
+/* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FPS_MCU_BOOT0 */
 };
 
 #endif