[coreboot-gerrit] Change in coreboot[master]: amd/gardenia: Fix most checkpatch errors
Martin Roth (Code Review)
gerrit at coreboot.org
Mon Jun 26 02:46:37 CEST 2017
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/20318 )
Change subject: amd/gardenia: Fix most checkpatch errors
......................................................................
amd/gardenia: Fix most checkpatch errors
Correct all checkpatch errors but leave two errors in place
that are caused by AMD typing.
Change-Id: I9daa374da76ff991de72d16bad0e8b586aa95525
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
Reviewed-on: https://review.coreboot.org/20318
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Martin Roth <martinroth at google.com>
---
M src/mainboard/amd/gardenia/BiosCallOuts.c
M src/mainboard/amd/gardenia/OemCustomize.c
M src/mainboard/amd/gardenia/acpi_tables.c
M src/mainboard/amd/gardenia/dsdt.asl
M src/mainboard/amd/gardenia/fchec.c
M src/mainboard/amd/gardenia/irq_tables.c
M src/mainboard/amd/gardenia/mainboard.c
M src/mainboard/amd/gardenia/mptable.c
M src/mainboard/amd/gardenia/romstage.c
9 files changed, 131 insertions(+), 116 deletions(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c
index f8d02a5..b82f61d 100644
--- a/src/mainboard/amd/gardenia/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c
@@ -28,10 +28,10 @@
#include <dimmSpd.h>
#include <agesawrapper.h>
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
+static AGESA_STATUS Fch_Oem_config(UINT32 Func,
+ UINT32 FchData, VOID *ConfigPtr);
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
+const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
@@ -83,7 +83,8 @@
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
if (StdHeader->Func == AMD_INIT_RESET) {
- FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
+ FCH_RESET_DATA_BLOCK *FchParams_reset =
+ (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
FchParams_reset->FchReset.SataEnable = hudson_sata_enable();
FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();
@@ -102,7 +103,8 @@
FchParams_env->Usb.Xhci0Enable = FALSE;
#endif
FchParams_env->Usb.Xhci1Enable = FALSE;
- FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */
+ /* 8: If USB3 port is unremoveable. */
+ FchParams_env->Usb.USB30PortInit = 8;
/* SATA configuration */
FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c
index 5f9f501..47e332e 100644
--- a/src/mainboard/amd/gardenia/OemCustomize.c
+++ b/src/mainboard/amd/gardenia/OemCustomize.c
@@ -17,12 +17,13 @@
#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
-static const PCIe_PORT_DESCRIPTOR PortList [] = {
- /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+ /* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 4, 7),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+ 2, 1,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -31,8 +32,9 @@
/* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 0, 1),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 2,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 0, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
+ 2, 2,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -40,8 +42,9 @@
},
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 1, 1),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 3,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
+ 2, 3,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -50,8 +53,9 @@
/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+ 2, 4,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -60,8 +64,9 @@
/* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */
{
DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+ 2, 5,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
@@ -70,24 +75,24 @@
/* Initialize Port descriptor (PCIe port, Lane 1, D2F3) for M.2 */
};
-static const PCIe_DDI_DESCRIPTOR DdiList [] = {
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* DDI0 - eDP */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1)
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
},
/* DDI1 - DP */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
},
/* DDI2 - HDMI */
{
DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3)
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
},
};
@@ -98,8 +103,7 @@
.DdiLinkList = DdiList
};
-static const UINT32 AzaliaCodecAlc286Table[] =
-{
+static const UINT32 AzaliaCodecAlc286Table[] = {
0x00172051, 0x001721C7, 0x00172222, 0x00172310,
0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00,
0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7,
@@ -120,19 +124,18 @@
0xffffffff
};
-CONST CODEC_VERB_TABLE_LIST CodecTableList[] =
-{
+CONST CODEC_VERB_TABLE_LIST CodecTableList[] = {
{ (UINT32) 0x10ec0286, AzaliaCodecAlc286Table},
{ (UINT32) 0x0FFFFFFFF, (UINT32 *)0x0FFFFFFFF}
};
-/*---------------------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
- * This is the stub function will call the host environment through the binary block
- * interface (call-out port) to provide a user hook opportunity
+ * This is the stub function will call the host environment through the
+ * binary block interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] **PeiServices
@@ -141,28 +144,30 @@
* @retval VOID
*
**/
-/*---------------------------------------------------------------------------------------*/
-VOID OemCustomizeInitEarly (
- IN OUT AMD_EARLY_PARAMS *InitEarly
- )
+/*---------------------------------------------------------------------------*/
+VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
- InitEarly->PlatformConfig.AzaliaCodecVerbTable = (UINT64)(UINTN)CodecTableList;
+ InitEarly->PlatformConfig.AzaliaCodecVerbTable =
+ (UINT64)(UINTN)CodecTableList;
}
static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
- MOTHER_BOARD_LAYERS (LAYERS_6),
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
+ MOTHER_BOARD_LAYERS(LAYERS_6),
+ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
+ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+ ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+ CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,
+ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
PSO_END
};
void OemPostParams(AMD_POST_PARAMS *PostParams)
{
- PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
+ PostParams->MemConfig.PlatformMemoryConfiguration =
+ (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
}
diff --git a/src/mainboard/amd/gardenia/acpi_tables.c b/src/mainboard/amd/gardenia/acpi_tables.c
index 1b4f90c..f55d9ce 100644
--- a/src/mainboard/amd/gardenia/acpi_tables.c
+++ b/src/mainboard/amd/gardenia/acpi_tables.c
@@ -34,24 +34,25 @@
current = acpi_create_madt_lapics(current);
/* Write Kern IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
- IO_APIC_ADDR, 0);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
+ CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
/* TODO: Remove the hardcode */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
- IO_APIC2_ADDR, 24);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
+ CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
+ current += acpi_create_madt_irqoverride(
+ (acpi_madt_irqoverride_t *)current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride(
+ (acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edge-triggered, Active high */
/* create all subtables for processors */
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
+ 0xff, 5, 1);
/* 1: LINT1 connect to NMI */
return current;
diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl
index 2245ea2..77e6230 100644
--- a/src/mainboard/amd/gardenia/dsdt.asl
+++ b/src/mainboard/amd/gardenia/dsdt.asl
@@ -23,7 +23,7 @@
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+ /* #include <arch/x86/acpi/debug.asl> */ /* as needed */
/* Globals for the platform */
#include "acpi/mainboard.asl"
@@ -48,7 +48,7 @@
/* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl>
- /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ /* IRQ Routing mapping for this platform (in \_SB scope) */
#include "acpi/routing.asl"
Device(PWRB) {
diff --git a/src/mainboard/amd/gardenia/fchec.c b/src/mainboard/amd/gardenia/fchec.c
index 532db79..aca3a9e 100644
--- a/src/mainboard/amd/gardenia/fchec.c
+++ b/src/mainboard/amd/gardenia/fchec.c
@@ -15,7 +15,7 @@
#include "fchec.h"
-void agesawrapper_fchecfancontrolservice()
+void agesawrapper_fchecfancontrolservice(void)
{
FCH_DATA_BLOCK LateParams;
@@ -26,36 +26,38 @@
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0xc6;
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
- LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
+ /* SMBUS Address for SMBUS based temperature sensor */
+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98;
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
- LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */
+ /* PWM steping rate in unit of PWM level percentage */
+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01;
LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
/* IMC Fan Policy temperature thresholds */
LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold in Celsius */
- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 threshold in Celsius */
- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 threshold in Celsius */
- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
- LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold */
+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 in oC */
+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 in oC */
+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 undefined */
+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 undefined */
+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 undefined */
+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 undefined */
+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 undefined */
+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*crit threshold */
LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
/* IMC Fan Policy PWM Settings */
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percentage */
- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percentage */
- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percentage */
- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percent */
+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percent */
+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percent */
+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percent */
+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percent */
+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percent */
+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percent */
+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percent */
LateParams.Imc.EcStruct.IMCFUNSupportBitMap = 0x111;
diff --git a/src/mainboard/amd/gardenia/irq_tables.c b/src/mainboard/amd/gardenia/irq_tables.c
index dd24f73..e8b906e 100644
--- a/src/mainboard/amd/gardenia/irq_tables.c
+++ b/src/mainboard/amd/gardenia/irq_tables.c
@@ -92,9 +92,8 @@
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
+ if (sum != pirq->checksum)
pirq->checksum = sum;
- }
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c
index 9470296..bd9f06c 100644
--- a/src/mainboard/amd/gardenia/mainboard.c
+++ b/src/mainboard/amd/gardenia/mainboard.c
@@ -31,41 +31,41 @@
* MP Tables. TODO: Make ACPI use these values too.
*/
const u8 mainboard_picr_data[] = {
- [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
- [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,
- [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
- [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,
- [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,
- [0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
- [0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F,
- [0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
- [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
- [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+ [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F,
+ [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
+ [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,
+ [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
+ [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
};
const u8 mainboard_intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,
- [0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,
- [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
- [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,
- [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,
- [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00,
- [0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
- [0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,
+ [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
+ [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
+ [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
+ [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
+ [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
/* PIRQ Setup */
@@ -82,7 +82,8 @@
*************************************************/
static void gardenia_enable(device_t dev)
{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ printk(BIOS_INFO, "Mainboard "
+ CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c
index 0d9064f..f32b8da 100644
--- a/src/mainboard/amd/gardenia/mptable.c
+++ b/src/mainboard/amd/gardenia/mptable.c
@@ -26,7 +26,7 @@
#include <soc/hudson.h>
#include <amd_pci_util.h>
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
@@ -75,16 +75,20 @@
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ smp_write_lintsrc(mc, (type), \
+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
+ (intr), (apicid), (pin))
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+ smp_write_intsrc(mc, mp_INT, \
+ MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
+ (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
@@ -146,7 +150,7 @@
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index 678e1fb..cd90494 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -44,7 +44,8 @@
/* Halt if there was a built in self test failure */
post_code(0x34);
- report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */
+ /* Mask bit 31. One result of Silicon Observation */
+ report_bist_failure(bist & 0x7FFFFFFF);
/* Load MPB */
val = cpuid_eax(1);
--
To view, visit https://review.coreboot.org/20318
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I9daa374da76ff991de72d16bad0e8b586aa95525
Gerrit-Change-Number: 20318
Gerrit-PatchSet: 2
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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