[coreboot-gerrit] Change in coreboot[master]: soc/stoneyridge: Remove FCH PCIe support

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/20319


Change subject: soc/stoneyridge: Remove FCH PCIe support
......................................................................

soc/stoneyridge: Remove FCH PCIe support

Remove the pcie.c file.  Historically PCIe lanes have been
available from the Gfx and/or the FCH.  The integrated FCH in
this APU has no PCIe available.

BUG=chrome-os-partner:62580062

Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/Makefile.inc
D src/soc/amd/stoneyridge/pcie.c
2 files changed, 0 insertions(+), 62 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/20319/1

diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index bc128a1..59fbbbe 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -59,7 +59,6 @@
 ramstage-y += lpc.c
 ramstage-y += model_15_init.c
 ramstage-y += northbridge.c
-ramstage-y += pcie.c
 ramstage-y += reset.c
 ramstage-y += sata.c
 ramstage-y += sd.c
diff --git a/src/soc/amd/stoneyridge/pcie.c b/src/soc/amd/stoneyridge/pcie.c
deleted file mode 100644
index 92b0a50..0000000
--- a/src/soc/amd/stoneyridge/pcie.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <soc/hudson.h>
-
-static void pcie_init(struct device *dev)
-{
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = 0,
-};
-
-static struct device_operations pci_ops = {
-	.read_resources = pci_bus_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init = pcie_init,
-	.scan_bus = pci_scan_bridge,
-	.reset_bus = pci_bus_reset,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver pciea_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_PCIEA,
-};
-
-static const struct pci_driver pcieb_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_PCIEB,
-};
-static const struct pci_driver pciec_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_PCIEC,
-};
-static const struct pci_driver pcied_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_PCIED,
-};

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778
Gerrit-Change-Number: 20319
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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