<p>Martin Roth <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/20318">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/gardenia: Fix most checkpatch errors<br><br>Correct all checkpatch errors but leave two errors in place<br>that are caused by AMD typing.<br><br>Change-Id: I9daa374da76ff991de72d16bad0e8b586aa95525<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>Reviewed-on: https://review.coreboot.org/20318<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Martin Roth <martinroth@google.com><br>---<br>M src/mainboard/amd/gardenia/BiosCallOuts.c<br>M src/mainboard/amd/gardenia/OemCustomize.c<br>M src/mainboard/amd/gardenia/acpi_tables.c<br>M src/mainboard/amd/gardenia/dsdt.asl<br>M src/mainboard/amd/gardenia/fchec.c<br>M src/mainboard/amd/gardenia/irq_tables.c<br>M src/mainboard/amd/gardenia/mainboard.c<br>M src/mainboard/amd/gardenia/mptable.c<br>M src/mainboard/amd/gardenia/romstage.c<br>9 files changed, 131 insertions(+), 116 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c<br>index f8d02a5..b82f61d 100644<br>--- a/src/mainboard/amd/gardenia/BiosCallOuts.c<br>+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c<br>@@ -28,10 +28,10 @@<br> #include <dimmSpd.h><br> #include <agesawrapper.h><br> <br>-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);<br>+static AGESA_STATUS Fch_Oem_config(UINT32 Func,<br>+ UINT32 FchData, VOID *ConfigPtr);<br> <br>-const BIOS_CALLOUT_STRUCT BiosCallouts[] =<br>-{<br>+const BIOS_CALLOUT_STRUCT BiosCallouts[] = {<br> {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },<br> {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },<br> {AGESA_LOCATE_BUFFER, agesa_LocateBuffer },<br>@@ -83,7 +83,8 @@<br> AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;<br> <br> if (StdHeader->Func == AMD_INIT_RESET) {<br>- FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;<br>+ FCH_RESET_DATA_BLOCK *FchParams_reset =<br>+ (FCH_RESET_DATA_BLOCK *)FchData;<br> printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");<br> FchParams_reset->FchReset.SataEnable = hudson_sata_enable();<br> FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();<br>@@ -102,7 +103,8 @@<br> FchParams_env->Usb.Xhci0Enable = FALSE;<br> #endif<br> FchParams_env->Usb.Xhci1Enable = FALSE;<br>- FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */<br>+ /* 8: If USB3 port is unremoveable. */<br>+ FchParams_env->Usb.USB30PortInit = 8;<br> <br> /* SATA configuration */<br> FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;<br>diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c<br>index 5f9f501..47e332e 100644<br>--- a/src/mainboard/amd/gardenia/OemCustomize.c<br>+++ b/src/mainboard/amd/gardenia/OemCustomize.c<br>@@ -17,12 +17,13 @@<br> #include <PlatformMemoryConfiguration.h><br> <br> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE<br>-static const PCIe_PORT_DESCRIPTOR PortList [] = {<br>- /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */<br>+static const PCIe_PORT_DESCRIPTOR PortList[] = {<br>+ /* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */<br> {<br> 0,<br>- PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 4, 7),<br>- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,<br>+ 2, 1,<br> HotplugDisabled,<br> PcieGenMaxSupported,<br> PcieGenMaxSupported,<br>@@ -31,8 +32,9 @@<br> /* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */<br> {<br> 0,<br>- PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 0, 1),<br>- PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 2,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 0, 1),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,<br>+ 2, 2,<br> HotplugDisabled,<br> PcieGenMaxSupported,<br> PcieGenMaxSupported,<br>@@ -40,8 +42,9 @@<br> },<br> {<br> 0,<br>- PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 1, 1),<br>- PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 3,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,<br>+ 2, 3,<br> HotplugDisabled,<br> PcieGenMaxSupported,<br> PcieGenMaxSupported,<br>@@ -50,8 +53,9 @@<br> /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */<br> {<br> 0,<br>- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),<br>- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,<br>+ 2, 4,<br> HotplugDisabled,<br> PcieGenMaxSupported,<br> PcieGenMaxSupported,<br>@@ -60,8 +64,9 @@<br> /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */<br> {<br> DESCRIPTOR_TERMINATE_LIST,<br>- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),<br>- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,<br>+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),<br>+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,<br>+ 2, 5,<br> HotplugDisabled,<br> PcieGenMaxSupported,<br> PcieGenMaxSupported,<br>@@ -70,24 +75,24 @@<br> /* Initialize Port descriptor (PCIe port, Lane 1, D2F3) for M.2 */<br> };<br> <br>-static const PCIe_DDI_DESCRIPTOR DdiList [] = {<br>+static const PCIe_DDI_DESCRIPTOR DdiList[] = {<br> /* DDI0 - eDP */<br> {<br> 0,<br>- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),<br>- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1)<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),<br>+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)<br> },<br> /* DDI1 - DP */<br> {<br> 0,<br>- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),<br>- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),<br>+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)<br> },<br> /* DDI2 - HDMI */<br> {<br> DESCRIPTOR_TERMINATE_LIST,<br>- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),<br>- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3)<br>+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),<br>+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)<br> },<br> };<br> <br>@@ -98,8 +103,7 @@<br> .DdiLinkList = DdiList<br> };<br> <br>-static const UINT32 AzaliaCodecAlc286Table[] =<br>-{<br>+static const UINT32 AzaliaCodecAlc286Table[] = {<br> 0x00172051, 0x001721C7, 0x00172222, 0x00172310,<br> 0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00,<br> 0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7,<br>@@ -120,19 +124,18 @@<br> 0xffffffff<br> };<br> <br>-CONST CODEC_VERB_TABLE_LIST CodecTableList[] =<br>-{<br>+CONST CODEC_VERB_TABLE_LIST CodecTableList[] = {<br> { (UINT32) 0x10ec0286, AzaliaCodecAlc286Table},<br> { (UINT32) 0x0FFFFFFFF, (UINT32 *)0x0FFFFFFFF}<br> };<br> <br>-/*---------------------------------------------------------------------------------------*/<br>+/*---------------------------------------------------------------------------*/<br> /**<br> * OemCustomizeInitEarly<br> *<br> * Description:<br>- * This is the stub function will call the host environment through the binary block<br>- * interface (call-out port) to provide a user hook opportunity<br>+ * This is the stub function will call the host environment through the<br>+ * binary block interface (call-out port) to provide a user hook opportunity<br> *<br> * Parameters:<br> * @param[in] **PeiServices<br>@@ -141,28 +144,30 @@<br> * @retval VOID<br> *<br> **/<br>-/*---------------------------------------------------------------------------------------*/<br>-VOID OemCustomizeInitEarly (<br>- IN OUT AMD_EARLY_PARAMS *InitEarly<br>- )<br>+/*---------------------------------------------------------------------------*/<br>+VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)<br> {<br> InitEarly->GnbConfig.PcieComplexList = &PcieComplex;<br>- InitEarly->PlatformConfig.AzaliaCodecVerbTable = (UINT64)(UINTN)CodecTableList;<br>+ InitEarly->PlatformConfig.AzaliaCodecVerbTable =<br>+ (UINT64)(UINTN)CodecTableList;<br> }<br> <br> static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {<br> DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),<br>- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),<br>- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),<br>- MOTHER_BOARD_LAYERS (LAYERS_6),<br>- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),<br>- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),<br>- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),<br>- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),<br>+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),<br>+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),<br>+ MOTHER_BOARD_LAYERS(LAYERS_6),<br>+ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,<br>+ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),<br>+ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),<br>+ ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),<br>+ CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,<br>+ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),<br> PSO_END<br> };<br> <br> void OemPostParams(AMD_POST_PARAMS *PostParams)<br> {<br>- PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;<br>+ PostParams->MemConfig.PlatformMemoryConfiguration =<br>+ (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;<br> }<br>diff --git a/src/mainboard/amd/gardenia/acpi_tables.c b/src/mainboard/amd/gardenia/acpi_tables.c<br>index 1b4f90c..f55d9ce 100644<br>--- a/src/mainboard/amd/gardenia/acpi_tables.c<br>+++ b/src/mainboard/amd/gardenia/acpi_tables.c<br>@@ -34,24 +34,25 @@<br> current = acpi_create_madt_lapics(current);<br> <br> /* Write Kern IOAPIC, only one */<br>- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,<br>- IO_APIC_ADDR, 0);<br>+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,<br>+ CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);<br> <br> /* TODO: Remove the hardcode */<br>- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,<br>- IO_APIC2_ADDR, 24);<br>+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,<br>+ CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24);<br> <br>- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)<br>- current, 0, 0, 2, 0);<br>- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)<br>- current, 0, 9, 9, 0xF);<br>+ current += acpi_create_madt_irqoverride(<br>+ (acpi_madt_irqoverride_t *)current, 0, 0, 2, 0);<br>+ current += acpi_create_madt_irqoverride(<br>+ (acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xF);<br> /* 0: mean bus 0--->ISA */<br> /* 0: PIC 0 */<br> /* 2: APIC 2 */<br> /* 5 mean: 0101 --> Edge-triggered, Active high */<br> <br> /* create all subtables for processors */<br>- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);<br>+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,<br>+ 0xff, 5, 1);<br> /* 1: LINT1 connect to NMI */<br> <br> return current;<br>diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl<br>index 2245ea2..77e6230 100644<br>--- a/src/mainboard/amd/gardenia/dsdt.asl<br>+++ b/src/mainboard/amd/gardenia/dsdt.asl<br>@@ -23,7 +23,7 @@<br> 0x00010001 /* OEM Revision */<br> )<br> { /* Start of ASL file */<br>- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */<br>+ /* #include <arch/x86/acpi/debug.asl> */ /* as needed */<br> <br> /* Globals for the platform */<br> #include "acpi/mainboard.asl"<br>@@ -48,7 +48,7 @@<br> /* global utility methods expected within the \_SB scope */<br> #include <arch/x86/acpi/globutil.asl><br> <br>- /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */<br>+ /* IRQ Routing mapping for this platform (in \_SB scope) */<br> #include "acpi/routing.asl"<br> <br> Device(PWRB) {<br>diff --git a/src/mainboard/amd/gardenia/fchec.c b/src/mainboard/amd/gardenia/fchec.c<br>index 532db79..aca3a9e 100644<br>--- a/src/mainboard/amd/gardenia/fchec.c<br>+++ b/src/mainboard/amd/gardenia/fchec.c<br>@@ -15,7 +15,7 @@<br> <br> #include "fchec.h"<br> <br>-void agesawrapper_fchecfancontrolservice()<br>+void agesawrapper_fchecfancontrolservice(void)<br> {<br> FCH_DATA_BLOCK LateParams;<br> <br>@@ -26,36 +26,38 @@<br> LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0xc6;<br> LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;<br> LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;<br>- LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */<br>+ /* SMBUS Address for SMBUS based temperature sensor */<br>+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98;<br> LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;<br>- LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */<br>+ /* PWM steping rate in unit of PWM level percentage */<br>+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01;<br> LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;<br> <br> /* IMC Fan Policy temperature thresholds */<br> LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;<br> LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */<br>- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold in Celsius */<br>- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 threshold in Celsius */<br>- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 threshold in Celsius */<br>- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */<br>- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */<br>- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */<br>- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */<br>- LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */<br>- LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 in oC */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 in oC */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 undefined */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 undefined */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 undefined */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 undefined */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 undefined */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*crit threshold */<br> LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;<br> <br> /* IMC Fan Policy PWM Settings */<br> LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;<br> LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */<br>- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percentage */<br>- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percentage */<br>- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percentage */<br>- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */<br>- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */<br>- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */<br>- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */<br>- LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percent */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percent */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percent */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percent */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percent */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percent */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percent */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percent */<br> <br> LateParams.Imc.EcStruct.IMCFUNSupportBitMap = 0x111;<br> <br>diff --git a/src/mainboard/amd/gardenia/irq_tables.c b/src/mainboard/amd/gardenia/irq_tables.c<br>index dd24f73..e8b906e 100644<br>--- a/src/mainboard/amd/gardenia/irq_tables.c<br>+++ b/src/mainboard/amd/gardenia/irq_tables.c<br>@@ -92,9 +92,8 @@<br> <br> sum = pirq->checksum - sum;<br> <br>- if (sum != pirq->checksum) {<br>+ if (sum != pirq->checksum)<br> pirq->checksum = sum;<br>- }<br> <br> printk(BIOS_INFO, "write_pirq_routing_table done.\n");<br> <br>diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c<br>index 9470296..bd9f06c 100644<br>--- a/src/mainboard/amd/gardenia/mainboard.c<br>+++ b/src/mainboard/amd/gardenia/mainboard.c<br>@@ -31,41 +31,41 @@<br> * MP Tables. TODO: Make ACPI use these values too.<br> */<br> const u8 mainboard_picr_data[] = {<br>- [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,<br>- [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,<br>- [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,<br>- [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>- [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,<br>- [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>- [0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,<br>- [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>- [0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,<br>- [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>- [0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,<br>- [0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,<br>- [0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F,<br>- [0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,<br>- [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,<br>- [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,<br>+ [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F,<br>+ [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,<br>+ [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F,<br>+ [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,<br>+ [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,<br>+ [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,<br>+ [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,<br>+ [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,<br>+ [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,<br>+ [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,<br>+ [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,<br> };<br> <br> const u8 mainboard_intr_data[] = {<br>- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,<br>- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,<br>- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,<br>- [0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,<br>- [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,<br>- [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>- [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,<br>- [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>- [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,<br>- [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>- [0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,<br>- [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>- [0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00,<br>- [0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>- [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,<br>- [0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,<br>+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,<br>+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,<br>+ [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,<br>+ [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,<br>+ [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,<br>+ [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br>+ [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,<br>+ [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,<br> };<br> <br> /* PIRQ Setup */<br>@@ -82,7 +82,8 @@<br> *************************************************/<br> static void gardenia_enable(device_t dev)<br> {<br>- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");<br>+ printk(BIOS_INFO, "Mainboard "<br>+ CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");<br> <br> /* Initialize the PIRQ data structures for consumption */<br> pirq_setup();<br>diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c<br>index 0d9064f..f32b8da 100644<br>--- a/src/mainboard/amd/gardenia/mptable.c<br>+++ b/src/mainboard/amd/gardenia/mptable.c<br>@@ -26,7 +26,7 @@<br> #include <soc/hudson.h><br> #include <amd_pci_util.h><br> <br>-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)<br>+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)<br> {<br> mc->mpc_length += length;<br> mc->mpc_entry_count++;<br>@@ -75,16 +75,20 @@<br> <br> smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);<br> <br>- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */<br>+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */<br> #define IO_LOCAL_INT(type, intr, apicid, pin) \<br>- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));<br>+ smp_write_lintsrc(mc, (type), \<br>+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \<br>+ (intr), (apicid), (pin))<br> mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);<br> <br> /* PCI interrupts are level triggered, and are<br> * associated with a specific bus/device/function tuple.<br> */<br> #define PCI_INT(bus, dev, int_sign, pin) \<br>- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))<br>+ smp_write_intsrc(mc, mp_INT, \<br>+ MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \<br>+ (((dev)<<2)|(int_sign)), ioapic_id, (pin))<br> <br> /* Internal VGA */<br> PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);<br>@@ -146,7 +150,7 @@<br> /* FCH PCIe PortD */<br> PCI_INT(0x0, 0x15, 0x3, 0x13);<br> <br>- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */<br>+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */<br> IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);<br> IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);<br> /* There is no extension information... */<br>diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c<br>index 678e1fb..cd90494 100644<br>--- a/src/mainboard/amd/gardenia/romstage.c<br>+++ b/src/mainboard/amd/gardenia/romstage.c<br>@@ -44,7 +44,8 @@<br> <br> /* Halt if there was a built in self test failure */<br> post_code(0x34);<br>- report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */<br>+ /* Mask bit 31. One result of Silicon Observation */<br>+ report_bist_failure(bist & 0x7FFFFFFF);<br> <br> /* Load MPB */<br> val = cpuid_eax(1);<br></pre><p>To view, visit <a href="https://review.coreboot.org/20318">change 20318</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20318"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I9daa374da76ff991de72d16bad0e8b586aa95525 </div>
<div style="display:none"> Gerrit-Change-Number: 20318 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>