[coreboot-gerrit] New patch to review for coreboot: cpu/intel/speedstep/acpi.c: Add Netburst and Pentium 4 CPUs
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Jan 2 21:16:16 CET 2017
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18019
-gerrit
commit 8e259c92247e7de72054e9feb4aaaeb783f35136
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Jan 2 21:00:59 2017 +0100
cpu/intel/speedstep/acpi.c: Add Netburst and Pentium 4 CPUs
MSR(0x2c) provides information abour FSB frequency
Change-Id: I42b0dcfdd62e07422acb77462aefc2d9b62fba19
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/cpu/intel/speedstep/acpi.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index d85e487..fb06cb6 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -49,7 +49,17 @@ static int determine_total_number_of_cores(void)
*/
static int get_fsb(void)
{
- const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7;
+ const u32 fsbcode;
+ const u32 eax;
+ msr_t msr;
+
+ if (((eax >> 8) & 0xf) == 0xf) {
+ msr = rdmsr(0x2c);
+ fsbcode = (msr.lo >> 16) & 7;
+ } else {
+ fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7;
+ }
+
switch (fsbcode) {
case 0: return 800; /* / 3 == 266 */
case 1: return 400; /* / 3 == 133 */
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