[coreboot-gerrit] Change in coreboot[master]: soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update.

[Divya Chellappa (Code Review)]

Divya Chellappa has uploaded this change for review. ( https://review.coreboot.org/22947


Change subject: soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update.
......................................................................

soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update.

There is a new UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to
configure clock source(s) of PCIe Root Ports. This UPD is used
to disable clock source(s) of disabled PCIe Root Port which
has active device connected.

CQ-DEPEND=CL:22629,CL:22899
BUG=b:70252901
BRANCH=None
TEST= Performed the following
1. Build and boot soraka
2. Verified PCIe devices list using lspci
3. FULL BAT on soraka

Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Signed-off-by: Divya Chellap <divya.chellappa at intel.com>
---
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/chip_fsp20.c
2 files changed, 10 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/22947/1

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 8540e21..64371ca 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -199,6 +199,8 @@
 	 */
 	u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];
 
+	u8 PcieRpClkSrcNumber[CONFIG_MAX_ROOT_PORTS];
+
 	/*
 	 * Enable/Disable AER (Advanced Error Reporting) for Root Port
 	 * 0: Disable AER
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 96c3b60..be60bfa 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -166,6 +166,14 @@
 	memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
 	       sizeof(params->PcieRpLtrEnable));
 
+	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++)
+	{
+		if (config->PcieRpClkReqSupport[i])
+			params->PcieRpClkSrcNumber[i] = config->PcieRpClkSrcNumber[i];
+		else
+			params->PcieRpClkSrcNumber[i] = 0x1F;
+	}
+
 	/* disable Legacy PME */
 	memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Gerrit-Change-Number: 22947
Gerrit-PatchSet: 1
Gerrit-Owner: Divya Chellappa <divya.chellappa at intel.com>
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