<p>Divya Chellappa has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22947">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update.<br><br>There is a new UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to<br>configure clock source(s) of PCIe Root Ports. This UPD is used<br>to disable clock source(s) of disabled PCIe Root Port which<br>has active device connected.<br><br>CQ-DEPEND=CL:22629,CL:22899<br>BUG=b:70252901<br>BRANCH=None<br>TEST= Performed the following<br>1. Build and boot soraka<br>2. Verified PCIe devices list using lspci<br>3. FULL BAT on soraka<br><br>Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e<br>Signed-off-by: Divya Chellap <divya.chellappa@intel.com><br>---<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/chip_fsp20.c<br>2 files changed, 10 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/22947/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h</span><br><span>index 8540e21..64371ca 100644</span><br><span>--- a/src/soc/intel/skylake/chip.h</span><br><span>+++ b/src/soc/intel/skylake/chip.h</span><br><span>@@ -199,6 +199,8 @@</span><br><span>         */</span><br><span>  u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+     u8 PcieRpClkSrcNumber[CONFIG_MAX_ROOT_PORTS];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>      /*</span><br><span>    * Enable/Disable AER (Advanced Error Reporting) for Root Port</span><br><span>        * 0: Disable AER</span><br><span>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>index 96c3b60..be60bfa 100644</span><br><span>--- a/src/soc/intel/skylake/chip_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>@@ -166,6 +166,14 @@</span><br><span>        memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,</span><br><span>              sizeof(params->PcieRpLtrEnable));</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+       for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+        {</span><br><span style="color: hsl(120, 100%, 40%);">+             if (config->PcieRpClkReqSupport[i])</span><br><span style="color: hsl(120, 100%, 40%);">+                        params->PcieRpClkSrcNumber[i] = config->PcieRpClkSrcNumber[i];</span><br><span style="color: hsl(120, 100%, 40%);">+          else</span><br><span style="color: hsl(120, 100%, 40%);">+                  params->PcieRpClkSrcNumber[i] = 0x1F;</span><br><span style="color: hsl(120, 100%, 40%);">+      }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>  /* disable Legacy PME */</span><br><span>     memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/22947">change 22947</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22947"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e </div>
<div style="display:none"> Gerrit-Change-Number: 22947 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Divya Chellappa <divya.chellappa@intel.com> </div>